DESIGN yimaqi
{
    PORT A input 
    {

    }
    PORT B input 
    {

    }
    PORT C input 
    {

    }
    PORT Y0 output 
    {

    }
    PORT Y1 output 
    {

    }
    PORT Y2 output 
    {

    }
    PORT Y3 output 
    {

    }
    PORT Y4 output 
    {

    }
    PORT Y5 output 
    {

    }
    PORT Y6 output 
    {

    }
    PORT Y7 output 
    {

    }
    ATTR CONFIGURATION string 13
CONFIG_HOLDER

    {
        ATTR $default string 1188
CFG_LST=$default
	VERSION=1.00
	OPTION=
	DEVICE=ispLSI1032E-100LJ84
	RESERVED_PINS=
	TIMING_ANALYSIS=0
	TA_MIN_DELAY=1
	TA_LSPATHS=1
	TA_MAX_PATHS=10
	TA_DEST_NODES=0
	TA_CLK_FREQ=ON
	TA_SETUP_HOLD=ON
	TA_CLK_TO_OUT=ON
	TA_TPD=ON
	TA_ENUM_PATHS=1
	TIMING_FILE=
	PARAMETER_FILE=
	USE_PARAMETER_FILE=OFF
	PERFORM_TA=ON
	PIN_FILE=
	PART_NAME=
	OUTPUT_FORM=
	EXTENDED_ROUTE=ON
	IGNORE_FIXED_PIN=OFF
	USE_GLOBAL_RESET=ON
	EXTENDED_LOGIC_OPT=OFF
	MIN_GLB=1
	CARRY_PIN_DIR=OFF
	CASE_SENSITIVE=OFF
	IGNORE_RESERVE_PIN=OFF
	SECURITY=OFF
	ISP=ON
	ISP_EXCEPT_Y2=OFF
	Y1_AS_RESET=OFF
	PULLUP=ON
	SLOWSLEW=OFF
	OPENDRAIN=OFF
	PORT_LST
		A	D=IN	L=	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		B	D=IN	L=	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		C	D=IN	L=	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		Y0	D=OUT	L=	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		Y1	D=OUT	L=	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		Y2	D=OUT	L=	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		Y3	D=OUT	L=	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		Y4	D=OUT	L=	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		Y5	D=OUT	L=	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		Y6	D=OUT	L=	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
		Y7	D=OUT	L=	P=-	S=-	C=OFF	O=-	DLY=-	V=-	
	PORT_END

	OPTION_LST
		EFFORT=2
		STRATEGY=d
		MAX_GLB_IN=16
		MAX_GLB_OUT=4
	OPTION_END
CFG_END


        {

        }

    }
    ATTR PART string 19
ispLSI1032E-100LJ84

    {

    }
    ATTR TECHNOLOGY string 4
pLSI

    {

    }
    ATTR STAT string 33
edif2laf 1.0 10.4.2006 20.22.20 1

    {

    }
    ATTR DESIGN string 6
yimaqi

    {

    }
    ATTR DESIGN_REV string 3
0.0

    {

    }

}