Frequency Analysis Report:
-------------------------

Design Name: UNTITLED
Part Name: ispLSI1032E-100LJ84

This report contains the maximum frequency at which the design
can be operated. It also lists the path that determines the
maximum frequency and the number of GLB levels. 
The remaining internal register paths and their frequencies
are also listed, if the source and the registers are driven
by the same reference clock.


Maximum Operating Frequency:    104 MHz

The clock period is 9.60.
Clock period = path delay + clock-to-output delay + setup time
  path delay:              6.60
  clock-to-output delay:   2.00
  setup time:              1.00


The following path determines the frequency: 

  Startpoint: GLB_RUN_Q_BLIF/Q0
              (edge-triggered flip-flop)
  Endpoint: GLB_RUN_Q_BLIF/D0
              (edge-triggered flip-flop)
  No. of GLB Levels: 1

Internal Register  Paths and Frequencies:

  Source              Source                  Destination       Destination             Clock     Frequency   # of GLB     
  Reference           Register                Reference         Register                Period      [MHz]     Levels       
  Clock               Name                    Clock             Name                     [ns]     
==----------------------------------------------------------------------------------------------------------------
  T1                  GLB_...BLIF *1/Q0       T1                GLB_...BLIF *1/D0        9.30      108       1    
  T1                  GLB_...BLIF *2/Q0       T1                GLB_...BLIF *1/D0        9.30      108       1    
  T1                  GLB_...BLIF *2/Q0       T1                GLB_...BLIF *2/D0        9.60      104       1    
  T1                  GLB_...BLIF *1/Q0       T1                GLB_...BLIF *2/D0        9.30      108       1    
==-------------------------------------------------------------------------------------------

Index Name Table
==----------------------------------------
    *1  GLB_STO_Q_BLIF
    *2  GLB_RUN_Q_BLIF
==----------------------------------------

Information for flip-flop:

  Global reset-to-output delay:   6.20
  Clock-to-output maximum delay: 2.00
  Clock-to-output minimum delay: 1.30
  User reset-to-output delay:     6.20
  Data-to-output delay:           0.00
  Setup time:                     1.00
  Hold time:                      5.30
  Pulse-width time:               4.00