MODEL
MODEL_VERSION "1.0";
DESIGN "untitled";
DATE "Tue Apr 18 19:25:22 2006";
VENDOR "Lattice Semiconductor Co. Ltd.";
PROGRAM "STAMP Model Generator";

/* port name and type */
INPUT IR4;
INPUT SWA;
INPUT CLR;
INPUT MF;
INPUT W4;
INPUT W3;
INPUT T1;
INPUT W2;
INPUT W1;
INPUT C;
INPUT XRESET;
INPUT IR7;
INPUT IR6;
INPUT SWC;
INPUT IR5;
INPUT SWB;
OUTPUT S1;
OUTPUT CEL;
OUTPUT S2;
OUTPUT AR1_INC;
OUTPUT LDPC;
OUTPUT M3;
OUTPUT LDAR1;
OUTPUT M4;
OUTPUT SW_BUS;
OUTPUT SKIP;
OUTPUT PC_ADD;
OUTPUT LDER;
OUTPUT ALU_BUS;
OUTPUT WRD;
OUTPUT LRW;
OUTPUT TJ;
OUTPUT RS_BUS;
OUTPUT S0;
OUTPUT LDIR;
OUTPUT LDDR1;

/* timing arc definitions */
SWA_LDDR1_delay: DELAY SWA LDDR1;
IR4_LDDR1_delay: DELAY IR4 LDDR1;
SWB_LDDR1_delay: DELAY SWB LDDR1;
IR5_LDDR1_delay: DELAY IR5 LDDR1;
SWC_LDDR1_delay: DELAY SWC LDDR1;
IR6_LDDR1_delay: DELAY IR6 LDDR1;
IR7_LDDR1_delay: DELAY IR7 LDDR1;
W2_LDDR1_delay: DELAY W2 LDDR1;
SWA_LDIR_delay: DELAY SWA LDIR;
SWB_LDIR_delay: DELAY SWB LDIR;
SWC_LDIR_delay: DELAY SWC LDIR;
W1_LDIR_delay: DELAY W1 LDIR;
W2_LDIR_delay: DELAY W2 LDIR;
SWA_S0_delay: DELAY SWA S0;
IR4_S0_delay: DELAY IR4 S0;
SWB_S0_delay: DELAY SWB S0;
IR5_S0_delay: DELAY IR5 S0;
SWC_S0_delay: DELAY SWC S0;
IR6_S0_delay: DELAY IR6 S0;
IR7_S0_delay: DELAY IR7 S0;
SWA_RS_BUS_delay: DELAY SWA RS_BUS;
IR4_RS_BUS_delay: DELAY IR4 RS_BUS;
SWB_RS_BUS_delay: DELAY SWB RS_BUS;
IR5_RS_BUS_delay: DELAY IR5 RS_BUS;
SWC_RS_BUS_delay: DELAY SWC RS_BUS;
IR6_RS_BUS_delay: DELAY IR6 RS_BUS;
IR7_RS_BUS_delay: DELAY IR7 RS_BUS;
W4_RS_BUS_delay: DELAY W4 RS_BUS;
W2_RS_BUS_delay: DELAY W2 RS_BUS;
SWA_TJ_delay: DELAY SWA TJ;
IR4_TJ_delay: DELAY IR4 TJ;
SWB_TJ_delay: DELAY SWB TJ;
IR5_TJ_delay: DELAY IR5 TJ;
SWC_TJ_delay: DELAY SWC TJ;
IR6_TJ_delay: DELAY IR6 TJ;
IR7_TJ_delay: DELAY IR7 TJ;
W4_TJ_delay: DELAY W4 TJ;
W1_TJ_delay: DELAY W1 TJ;
W2_TJ_delay: DELAY W2 TJ;
SWA_LRW_delay: DELAY SWA LRW;
IR4_LRW_delay: DELAY IR4 LRW;
SWB_LRW_delay: DELAY SWB LRW;
IR5_LRW_delay: DELAY IR5 LRW;
SWC_LRW_delay: DELAY SWC LRW;
IR6_LRW_delay: DELAY IR6 LRW;
IR7_LRW_delay: DELAY IR7 LRW;
W1_LRW_delay: DELAY W1 LRW;
W3_LRW_delay: DELAY W3 LRW;
SWA_WRD_delay: DELAY SWA WRD;
IR4_WRD_delay: DELAY IR4 WRD;
SWB_WRD_delay: DELAY SWB WRD;
IR5_WRD_delay: DELAY IR5 WRD;
SWC_WRD_delay: DELAY SWC WRD;
IR6_WRD_delay: DELAY IR6 WRD;
IR7_WRD_delay: DELAY IR7 WRD;
W4_WRD_delay: DELAY W4 WRD;
SWA_ALU_BUS_delay: DELAY SWA ALU_BUS;
IR4_ALU_BUS_delay: DELAY IR4 ALU_BUS;
SWB_ALU_BUS_delay: DELAY SWB ALU_BUS;
IR5_ALU_BUS_delay: DELAY IR5 ALU_BUS;
SWC_ALU_BUS_delay: DELAY SWC ALU_BUS;
IR6_ALU_BUS_delay: DELAY IR6 ALU_BUS;
IR7_ALU_BUS_delay: DELAY IR7 ALU_BUS;
W4_ALU_BUS_delay: DELAY W4 ALU_BUS;
W3_ALU_BUS_delay: DELAY W3 ALU_BUS;
SWA_LDER_delay: DELAY SWA LDER;
IR4_LDER_delay: DELAY IR4 LDER;
SWB_LDER_delay: DELAY SWB LDER;
IR5_LDER_delay: DELAY IR5 LDER;
SWC_LDER_delay: DELAY SWC LDER;
IR6_LDER_delay: DELAY IR6 LDER;
IR7_LDER_delay: DELAY IR7 LDER;
W3_LDER_delay: DELAY W3 LDER;
SWA_PC_ADD_delay: DELAY SWA PC_ADD;
IR4_PC_ADD_delay: DELAY IR4 PC_ADD;
SWB_PC_ADD_delay: DELAY SWB PC_ADD;
IR5_PC_ADD_delay: DELAY IR5 PC_ADD;
SWC_PC_ADD_delay: DELAY SWC PC_ADD;
IR6_PC_ADD_delay: DELAY IR6 PC_ADD;
IR7_PC_ADD_delay: DELAY IR7 PC_ADD;
W4_PC_ADD_delay: DELAY W4 PC_ADD;
C_PC_ADD_delay: DELAY C PC_ADD;
SWA_SKIP_delay: DELAY SWA SKIP;
SWB_SKIP_delay: DELAY SWB SKIP;
SWC_SKIP_delay: DELAY SWC SKIP;
W2_SKIP_delay: DELAY W2 SKIP;
IR4_SKIP_delay: DELAY IR4 SKIP;
IR5_SKIP_delay: DELAY IR5 SKIP;
IR6_SKIP_delay: DELAY IR6 SKIP;
IR7_SKIP_delay: DELAY IR7 SKIP;
W1_SKIP_delay: DELAY W1 SKIP;
SWA_SW_BUS_delay: DELAY SWA SW_BUS;
SWB_SW_BUS_delay: DELAY SWB SW_BUS;
SWC_SW_BUS_delay: DELAY SWC SW_BUS;
W3_SW_BUS_delay: DELAY W3 SW_BUS;
W1_SW_BUS_delay: DELAY W1 SW_BUS;
W4_SW_BUS_delay: DELAY W4 SW_BUS;
SWA_M4_delay: DELAY SWA M4;
IR4_M4_delay: DELAY IR4 M4;
SWB_M4_delay: DELAY SWB M4;
IR5_M4_delay: DELAY IR5 M4;
SWC_M4_delay: DELAY SWC M4;
IR6_M4_delay: DELAY IR6 M4;
IR7_M4_delay: DELAY IR7 M4;
W4_M4_delay: DELAY W4 M4;
SWA_LDAR1_delay: DELAY SWA LDAR1;
SWB_LDAR1_delay: DELAY SWB LDAR1;
W4_LDAR1_delay: DELAY W4 LDAR1;
IR5_LDAR1_delay: DELAY IR5 LDAR1;
SWC_LDAR1_delay: DELAY SWC LDAR1;
IR6_LDAR1_delay: DELAY IR6 LDAR1;
IR7_LDAR1_delay: DELAY IR7 LDAR1;
W1_LDAR1_delay: DELAY W1 LDAR1;
W2_LDAR1_delay: DELAY W2 LDAR1;
SWA_M3_delay: DELAY SWA M3;
SWB_M3_delay: DELAY SWB M3;
SWC_M3_delay: DELAY SWC M3;
W4_M3_delay: DELAY W4 M3;
SWA_LDPC_delay: DELAY SWA LDPC;
IR4_LDPC_delay: DELAY IR4 LDPC;
SWB_LDPC_delay: DELAY SWB LDPC;
IR5_LDPC_delay: DELAY IR5 LDPC;
SWC_LDPC_delay: DELAY SWC LDPC;
IR6_LDPC_delay: DELAY IR6 LDPC;
IR7_LDPC_delay: DELAY IR7 LDPC;
W4_LDPC_delay: DELAY W4 LDPC;
C_LDPC_delay: DELAY C LDPC;
SWA_AR1_INC_delay: DELAY SWA AR1_INC;
SWB_AR1_INC_delay: DELAY SWB AR1_INC;
SWC_AR1_INC_delay: DELAY SWC AR1_INC;
W4_AR1_INC_delay: DELAY W4 AR1_INC;
SWA_S2_delay: DELAY SWA S2;
IR4_S2_delay: DELAY IR4 S2;
SWB_S2_delay: DELAY SWB S2;
IR5_S2_delay: DELAY IR5 S2;
SWC_S2_delay: DELAY SWC S2;
IR6_S2_delay: DELAY IR6 S2;
IR7_S2_delay: DELAY IR7 S2;
SWA_CEL_delay: DELAY SWA CEL;
IR4_CEL_delay: DELAY IR4 CEL;
SWB_CEL_delay: DELAY SWB CEL;
IR5_CEL_delay: DELAY IR5 CEL;
SWC_CEL_delay: DELAY SWC CEL;
IR6_CEL_delay: DELAY IR6 CEL;
IR7_CEL_delay: DELAY IR7 CEL;
W3_CEL_delay: DELAY W3 CEL;
W1_CEL_delay: DELAY W1 CEL;
W4_CEL_delay: DELAY W4 CEL;
SWA_S1_delay: DELAY SWA S1;
SWB_S1_delay: DELAY SWB S1;
IR5_S1_delay: DELAY IR5 S1;
SWC_S1_delay: DELAY SWC S1;
IR6_S1_delay: DELAY IR6 S1;
IR7_S1_delay: DELAY IR7 S1;
CLR_LDDR1_delay: DELAY CLR LDDR1;
CLR_LDIR_delay: DELAY CLR LDIR;
CLR_S0_delay: DELAY CLR S0;
CLR_RS_BUS_delay: DELAY CLR RS_BUS;
CLR_TJ_delay: DELAY CLR TJ;
CLR_LRW_delay: DELAY CLR LRW;
CLR_WRD_delay: DELAY CLR WRD;
CLR_ALU_BUS_delay: DELAY CLR ALU_BUS;
CLR_LDER_delay: DELAY CLR LDER;
CLR_PC_ADD_delay: DELAY CLR PC_ADD;
CLR_SKIP_delay: DELAY CLR SKIP;
CLR_SW_BUS_delay: DELAY CLR SW_BUS;
CLR_M4_delay: DELAY CLR M4;
CLR_LDAR1_delay: DELAY CLR LDAR1;
CLR_M3_delay: DELAY CLR M3;
CLR_LDPC_delay: DELAY CLR LDPC;
CLR_AR1_INC_delay: DELAY CLR AR1_INC;
CLR_S2_delay: DELAY CLR S2;
CLR_CEL_delay: DELAY CLR CEL;
CLR_S1_delay: DELAY CLR S1;
MF_LDDR1_delay: DELAY MF LDDR1;
MF_LDIR_delay: DELAY MF LDIR;
MF_S0_delay: DELAY MF S0;
MF_RS_BUS_delay: DELAY MF RS_BUS;
MF_TJ_delay: DELAY MF TJ;
MF_LRW_delay: DELAY MF LRW;
MF_WRD_delay: DELAY MF WRD;
MF_ALU_BUS_delay: DELAY MF ALU_BUS;
MF_LDER_delay: DELAY MF LDER;
MF_PC_ADD_delay: DELAY MF PC_ADD;
MF_SKIP_delay: DELAY MF SKIP;
MF_SW_BUS_delay: DELAY MF SW_BUS;
MF_M4_delay: DELAY MF M4;
MF_LDAR1_delay: DELAY MF LDAR1;
MF_M3_delay: DELAY MF M3;
MF_LDPC_delay: DELAY MF LDPC;
MF_AR1_INC_delay: DELAY MF AR1_INC;
MF_S2_delay: DELAY MF S2;
MF_CEL_delay: DELAY MF CEL;
MF_S1_delay: DELAY MF S1;
T1_LDDR1_delay: DELAY T1 LDDR1;
T1_LDIR_delay: DELAY T1 LDIR;
T1_S0_delay: DELAY T1 S0;
T1_RS_BUS_delay: DELAY T1 RS_BUS;
T1_TJ_delay: DELAY T1 TJ;
T1_LRW_delay: DELAY T1 LRW;
T1_WRD_delay: DELAY T1 WRD;
T1_ALU_BUS_delay: DELAY T1 ALU_BUS;
T1_LDER_delay: DELAY T1 LDER;
T1_PC_ADD_delay: DELAY T1 PC_ADD;
T1_SKIP_delay: DELAY T1 SKIP;
T1_SW_BUS_delay: DELAY T1 SW_BUS;
T1_M4_delay: DELAY T1 M4;
T1_LDAR1_delay: DELAY T1 LDAR1;
T1_M3_delay: DELAY T1 M3;
T1_LDPC_delay: DELAY T1 LDPC;
T1_AR1_INC_delay: DELAY T1 AR1_INC;
T1_S2_delay: DELAY T1 S2;
T1_CEL_delay: DELAY T1 CEL;
T1_S1_delay: DELAY T1 S1;

/* timing check arc definitions */
W4_T1_setup: SETUP(POSEDGE) W4 T1;
W4_T1_hold: HOLD(POSEDGE) W4 T1;
W4_MF_setup: SETUP(POSEDGE) W4 MF;
W4_MF_hold: HOLD(POSEDGE) W4 MF;
W4_CLR_setup: SETUP(POSEDGE) W4 CLR;
W4_CLR_hold: HOLD(POSEDGE) W4 CLR;
CLR_T1_setup: SETUP(POSEDGE) CLR T1;
CLR_T1_hold: HOLD(POSEDGE) CLR T1;
CLR_MF_setup: SETUP(POSEDGE) CLR MF;
CLR_MF_hold: HOLD(POSEDGE) CLR MF;
CLR_CLR_setup: SETUP(POSEDGE) CLR CLR;
CLR_CLR_hold: HOLD(POSEDGE) CLR CLR;

ENDMODEL