/////////////////////////////////////////////////////////    module describe// name: 		hashoutput// function:	output the digest and the status// writer:		zy// data:		2006/03/07// version:		1.0// feature:		////////////////////////////////////////////////////////module hashoutput(clk,en,reset,wr,maskword,addr,digestin,lenerror,digestready,keyready,digestout,sha1int);input clk;input en;input reset;input wr;input [2:0] maskword;input [3:0] addr;input [159:0] digestin;input lenerror;input digestready;input keyready;output [31:0] digestout;output sha1int;reg [31:0] digestout;reg [2:0] statusreg;reg sha1int;reg keyreadyclr;reg lenerrorclr;reg digestreadyclr;always @(posedge clk)begin	if (reset)		statusreg<=0;	else if (digestready)		statusreg[0]<=1;	else if (lenerror)		statusreg[1]<=1;	else if (keyready)		statusreg[2]<=1;	else if ((statusreg[0])&&(addr==9)&&en)		statusreg[0]<=0;	else if ((statusreg[1])&&(addr==2)&&en)		statusreg[1]<=0;endalways @(posedge clk)begin	if (reset)		sha1int <= 0;	else if ((statusreg[2])&!keyreadyclr&(!maskword[2])|(statusreg[1])&!lenerrorclr&(!maskword[1])|(statusreg[0])&!digestreadyclr&(!maskword[0]))		sha1int <= 1;	else		sha1int <= 0;endalways @(posedge clk)begin	if (reset)		keyreadyclr <= 0;	else if (statusreg[2])		keyreadyclr <= 1;	else		keyreadyclr <= 0;endalways @(posedge clk)begin	if (reset)		lenerrorclr <= 0;	else if (statusreg[1])		lenerrorclr <= 1;	else		lenerrorclr <= 0;endalways @(posedge clk)begin	if (reset)		digestreadyclr <= 0;	else if (statusreg[0])		digestreadyclr <= 1;	else		digestreadyclr <= 0;endalways @(wr or addr or en or digestin or statusreg)begin	if ((wr)&&(en))		begin			case (addr)			4: digestout<={29'h0,statusreg};			5: digestout<=digestin[159:128];			6: digestout<=digestin[127:96];			7: digestout<=digestin[95:64];			8: digestout<=digestin[63:32];			9: digestout<=digestin[31:0];			default:digestout<=0;			endcase		end	else digestout<=0;endendmodule