{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "inclk register register temp\[0\] temp\[4\] 275.03 MHz Internal " "Info: Clock \"inclk\" Internal fmax is restricted to 275.03 MHz between source register \"temp\[0\]\" and destination register \"temp\[4\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.282 ns + Longest register register " "Info: + Longest register to register delay is 2.282 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp\[0\] 1 REG LC_X4_Y20_N1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y20_N1; Fanout = 4; REG Node = 'temp\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { temp[0] } "NODE_NAME" } } { "timedevider.vhd" "" { Text "C:/Documents and Settings/zhhf/桌面/2004011267_趙海富_無41/2004011267_趙海富_實驗四/timedevider.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.545 ns) + CELL(0.564 ns) 1.109 ns temp\[0\]~76 2 COMB LC_X4_Y20_N1 2 " "Info: 2: + IC(0.545 ns) + CELL(0.564 ns) = 1.109 ns; Loc. = LC_X4_Y20_N1; Fanout = 2; COMB Node = 'temp\[0\]~76'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.109 ns" { temp[0] temp[0]~76 } "NODE_NAME" } } { "timedevider.vhd" "" { Text "C:/Documents and Settings/zhhf/桌面/2004011267_趙海富_無41/2004011267_趙海富_實驗四/timedevider.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.187 ns temp\[1\]~77 3 COMB LC_X4_Y20_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.187 ns; Loc. = LC_X4_Y20_N2; Fanout = 2; COMB Node = 'temp\[1\]~77'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { temp[0]~76 temp[1]~77 } "NODE_NAME" } } { "timedevider.vhd" "" { Text "C:/Documents and Settings/zhhf/桌面/2004011267_趙海富_無41/2004011267_趙海富_實驗四/timedevider.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.265 ns temp\[2\]~78 4 COMB LC_X4_Y20_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.265 ns; Loc. = LC_X4_Y20_N3; Fanout = 2; COMB Node = 'temp\[2\]~78'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { temp[1]~77 temp[2]~78 } "NODE_NAME" } } { "timedevider.vhd" "" { Text "C:/Documents and Settings/zhhf/桌面/2004011267_趙海富_無41/2004011267_趙海富_實驗四/timedevider.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.443 ns temp\[3\]~79 5 COMB LC_X4_Y20_N4 2 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.443 ns; Loc. = LC_X4_Y20_N4; Fanout = 2; COMB Node = 'temp\[3\]~79'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.178 ns" { temp[2]~78 temp[3]~79 } "NODE_NAME" } } { "timedevider.vhd" "" { Text "C:/Documents and Settings/zhhf/桌面/2004011267_趙海富_無41/2004011267_趙海富_實驗四/timedevider.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 2.282 ns temp\[4\] 6 REG LC_X4_Y20_N5 4 " "Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 2.282 ns; Loc. = LC_X4_Y20_N5; Fanout = 4; REG Node = 'temp\[4\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.839 ns" { temp[3]~79 temp[4] } "NODE_NAME" } } { "timedevider.vhd" "" { Text "C:/Documents and Settings/zhhf/桌面/2004011267_趙海富_無41/2004011267_趙海富_實驗四/timedevider.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.737 ns ( 76.12 % ) " "Info: Total cell delay = 1.737 ns ( 76.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.545 ns ( 23.88 % ) " "Info: Total interconnect delay = 0.545 ns ( 23.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.282 ns" { temp[0] temp[0]~76 temp[1]~77 temp[2]~78 temp[3]~79 temp[4] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.282 ns" { temp[0] temp[0]~76 temp[1]~77 temp[2]~78 temp[3]~79 temp[4] } { 0.000ns 0.545ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"inclk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns inclk 1 CLK PIN_29 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 7; CLK Node = 'inclk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "timedevider.vhd" "" { Text "C:/Documents and Settings/zhhf/桌面/2004011267_趙海富_無41/2004011267_趙海富_實驗四/timedevider.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns temp\[4\] 2 REG LC_X4_Y20_N5 4 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X4_Y20_N5; Fanout = 4; REG Node = 'temp\[4\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.485 ns" { inclk temp[4] } "NODE_NAME" } } { "timedevider.vhd" "" { Text "C:/Documents and Settings/zhhf/桌面/2004011267_趙海富_無41/2004011267_趙海富_實驗四/timedevider.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { inclk temp[4] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { inclk inclk~out0 temp[4] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"inclk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns inclk 1 CLK PIN_29 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 7; CLK Node = 'inclk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "timedevider.vhd" "" { Text "C:/Documents and Settings/zhhf/桌面/2004011267_趙海富_無41/2004011267_趙海富_實驗四/timedevider.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns temp\[0\] 2 REG LC_X4_Y20_N1 4 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X4_Y20_N1; Fanout = 4; REG Node = 'temp\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.485 ns" { inclk temp[0] } "NODE_NAME" } } { "timedevider.vhd" "" { Text "C:/Documents and Settings/zhhf/桌面/2004011267_趙海富_無41/2004011267_趙海富_實驗四/timedevider.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { inclk temp[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { inclk inclk~out0 temp[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { inclk temp[4] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { inclk inclk~out0 temp[4] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { inclk temp[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { inclk inclk~out0 temp[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "timedevider.vhd" "" { Text "C:/Documents and Settings/zhhf/桌面/2004011267_趙海富_無41/2004011267_趙海富_實驗四/timedevider.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "timedevider.vhd" "" { Text "C:/Documents and Settings/zhhf/桌面/2004011267_趙海富_無41/2004011267_趙海富_實驗四/timedevider.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.282 ns" { temp[0] temp[0]~76 temp[1]~77 temp[2]~78 temp[3]~79 temp[4] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.282 ns" { temp[0] temp[0]~76 temp[1]~77 temp[2]~78 temp[3]~79 temp[4] } { 0.000ns 0.545ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.839ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { inclk temp[4] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { inclk inclk~out0 temp[4] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { inclk temp[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { inclk inclk~out0 temp[0] } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { temp[4] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { temp[4] } {  } {  } } } { "timedevider.vhd" "" { Text "C:/Documents and Settings/zhhf/桌面/2004011267_趙海富_無41/2004011267_趙海富_實驗四/timedevider.vhd" 18 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "inclk outclk outclk~reg0 6.580 ns register " "Info: tco from clock \"inclk\" to destination pin \"outclk\" through register \"outclk~reg0\" is 6.580 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk source 2.954 ns + Longest register " "Info: + Longest clock path from clock \"inclk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns inclk 1 CLK PIN_29 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 7; CLK Node = 'inclk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { inclk } "NODE_NAME" } } { "timedevider.vhd" "" { Text "C:/Documents and Settings/zhhf/桌面/2004011267_趙海富_無41/2004011267_趙海富_實驗四/timedevider.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns outclk~reg0 2 REG LC_X4_Y20_N0 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X4_Y20_N0; Fanout = 2; REG Node = 'outclk~reg0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.485 ns" { inclk outclk~reg0 } "NODE_NAME" } } { "timedevider.vhd" "" { Text "C:/Documents and Settings/zhhf/桌面/2004011267_趙海富_無41/2004011267_趙海富_實驗四/timedevider.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { inclk outclk~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { inclk inclk~out0 outclk~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "timedevider.vhd" "" { Text "C:/Documents and Settings/zhhf/桌面/2004011267_趙海富_無41/2004011267_趙海富_實驗四/timedevider.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.402 ns + Longest register pin " "Info: + Longest register to pin delay is 3.402 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns outclk~reg0 1 REG LC_X4_Y20_N0 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y20_N0; Fanout = 2; REG Node = 'outclk~reg0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { outclk~reg0 } "NODE_NAME" } } { "timedevider.vhd" "" { Text "C:/Documents and Settings/zhhf/桌面/2004011267_趙海富_無41/2004011267_趙海富_實驗四/timedevider.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.294 ns) + CELL(2.108 ns) 3.402 ns outclk 2 PIN PIN_237 0 " "Info: 2: + IC(1.294 ns) + CELL(2.108 ns) = 3.402 ns; Loc. = PIN_237; Fanout = 0; PIN Node = 'outclk'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.402 ns" { outclk~reg0 outclk } "NODE_NAME" } } { "timedevider.vhd" "" { Text "C:/Documents and Settings/zhhf/桌面/2004011267_趙海富_無41/2004011267_趙海富_實驗四/timedevider.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 61.96 % ) " "Info: Total cell delay = 2.108 ns ( 61.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.294 ns ( 38.04 % ) " "Info: Total interconnect delay = 1.294 ns ( 38.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.402 ns" { outclk~reg0 outclk } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.402 ns" { outclk~reg0 outclk } { 0.000ns 1.294ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.954 ns" { inclk outclk~reg0 } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.954 ns" { inclk inclk~out0 outclk~reg0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.402 ns" { outclk~reg0 outclk } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.402 ns" { outclk~reg0 outclk } { 0.000ns 1.294ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 06 15:29:52 2006 " "Info: Processing ended: Wed Sep 06 15:29:52 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}