; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[1]     ; temp[4]     ; inclk      ; inclk    ; None                        ; None                      ; 2.198 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[1]     ; temp[5]     ; inclk      ; inclk    ; None                        ; None                      ; 2.198 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[0]     ; outclk~reg0 ; inclk      ; inclk    ; None                        ; None                      ; 2.067 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[0]     ; temp[3]     ; inclk      ; inclk    ; None                        ; None                      ; 2.067 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[0]     ; temp[2]     ; inclk      ; inclk    ; None                        ; None                      ; 1.987 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[1]     ; temp[3]     ; inclk      ; inclk    ; None                        ; None                      ; 1.981 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[2]     ; temp[4]     ; inclk      ; inclk    ; None                        ; None                      ; 1.971 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[2]     ; temp[5]     ; inclk      ; inclk    ; None                        ; None                      ; 1.971 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[3]     ; temp[4]     ; inclk      ; inclk    ; None                        ; None                      ; 1.935 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[3]     ; temp[5]     ; inclk      ; inclk    ; None                        ; None                      ; 1.935 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[0]     ; temp[1]     ; inclk      ; inclk    ; None                        ; None                      ; 1.907 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[1]     ; temp[2]     ; inclk      ; inclk    ; None                        ; None                      ; 1.901 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[3]     ; outclk~reg0 ; inclk      ; inclk    ; None                        ; None                      ; 1.883 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[1]     ; outclk~reg0 ; inclk      ; inclk    ; None                        ; None                      ; 1.775 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[2]     ; temp[3]     ; inclk      ; inclk    ; None                        ; None                      ; 1.750 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[4]     ; temp[5]     ; inclk      ; inclk    ; None                        ; None                      ; 1.743 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[2]     ; outclk~reg0 ; inclk      ; inclk    ; None                        ; None                      ; 1.588 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[5]     ; outclk~reg0 ; inclk      ; inclk    ; None                        ; None                      ; 1.292 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[0]     ; temp[0]     ; inclk      ; inclk    ; None                        ; None                      ; 1.283 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[1]     ; temp[1]     ; inclk      ; inclk    ; None                        ; None                      ; 1.277 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[4]     ; outclk~reg0 ; inclk      ; inclk    ; None                        ; None                      ; 1.141 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[2]     ; temp[2]     ; inclk      ; inclk    ; None                        ; None                      ; 1.138 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[4]     ; temp[4]     ; inclk      ; inclk    ; None                        ; None                      ; 1.131 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[3]     ; temp[3]     ; inclk      ; inclk    ; None                        ; None                      ; 1.120 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; outclk~reg0 ; outclk~reg0 ; inclk      ; inclk    ; None                        ; None                      ; 0.847 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; temp[5]     ; temp[5]     ; inclk      ; inclk    ; None                        ; None                      ; 0.847 ns                ;
+-------+------------------------------------------------+-------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------+
; tco                                                                   ;
+-------+--------------+------------+-------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From        ; To     ; From Clock ;
+-------+--------------+------------+-------------+--------+------------+
; N/A   ; None         ; 6.580 ns   ; outclk~reg0 ; outclk ; inclk      ;
+-------+--------------+------------+-------------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Sep 06 15:29:51 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off timedevider -c timedevider --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "inclk" is an undefined clock
Info: Clock "inclk" Internal fmax is restricted to 275.03 MHz between source register "temp[0]" and destination register "temp[4]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.282 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y20_N1; Fanout = 4; REG Node = 'temp[0]'
            Info: 2: + IC(0.545 ns) + CELL(0.564 ns) = 1.109 ns; Loc. = LC_X4_Y20_N1; Fanout = 2; COMB Node = 'temp[0]~76'
            Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.187 ns; Loc. = LC_X4_Y20_N2; Fanout = 2; COMB Node = 'temp[1]~77'
            Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.265 ns; Loc. = LC_X4_Y20_N3; Fanout = 2; COMB Node = 'temp[2]~78'
            Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.443 ns; Loc. = LC_X4_Y20_N4; Fanout = 2; COMB Node = 'temp[3]~79'
            Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 2.282 ns; Loc. = LC_X4_Y20_N5; Fanout = 4; REG Node = 'temp[4]'
            Info: Total cell delay = 1.737 ns ( 76.12 % )
            Info: Total interconnect delay = 0.545 ns ( 23.88 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "inclk" to destination register is 2.954 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 7; CLK Node = 'inclk'
                Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X4_Y20_N5; Fanout = 4; REG Node = 'temp[4]'
                Info: Total cell delay = 2.180 ns ( 73.80 % )
                Info: Total interconnect delay = 0.774 ns ( 26.20 % )
            Info: - Longest clock path from clock "inclk" to source register is 2.954 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 7; CLK Node = 'inclk'
                Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X4_Y20_N1; Fanout = 4; REG Node = 'temp[0]'
                Info: Total cell delay = 2.180 ns ( 73.80 % )
                Info: Total interconnect delay = 0.774 ns ( 26.20 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "inclk" to destination pin "outclk" through register "outclk~reg0" is 6.580 ns
    Info: + Longest clock path from clock "inclk" to source register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 7; CLK Node = 'inclk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X4_Y20_N0; Fanout = 2; REG Node = 'outclk~reg0'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 3.402 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y20_N0; Fanout = 2; REG Node = 'outclk~reg0'
        Info: 2: + IC(1.294 ns) + CELL(2.108 ns) = 3.402 ns; Loc. = PIN_237; Fanout = 0; PIN Node = 'outclk'
        Info: Total cell delay = 2.108 ns ( 61.96 % )
        Info: Total interconnect delay = 1.294 ns ( 38.04 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Sep 06 15:29:52 2006
    Info: Elapsed time: 00:00:01