?? zhengliu.mdl
字號:
UseBusObject off
BusObject "BusObject"
NonVirtualBus off
}
Block {
BlockType Constant
}
Block {
BlockType DataTypeConversion
OutDataTypeMode "Inherit via back propagation"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
ConvertRealWorld "Real World Value (RWV)"
RndMeth "Zero"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Demux
Outputs "4"
DisplayOption "none"
BusSelectionMode off
}
Block {
BlockType DiscretePulseGenerator
PulseType "Sample based"
TimeSource "Use simulation time"
Amplitude "1"
Period "2"
PulseWidth "1"
PhaseDelay "0"
SampleTime "1"
VectorParams1D on
}
Block {
BlockType EnablePort
StatesWhenEnabling "held"
ShowOutputPort off
ZeroCross on
}
Block {
BlockType From
IconDisplay "Tag"
}
Block {
BlockType Gain
Gain "1"
Multiplication "Element-wise(K.*u)"
ParameterDataTypeMode "Same as input"
ParameterDataType "sfix(16)"
ParameterScalingMode "Best Precision: Matrix-wise"
ParameterScaling "2^0"
OutDataTypeMode "Same as input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Goto
IconDisplay "Tag"
}
Block {
BlockType Ground
}
Block {
BlockType Inport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchByCopyingInsideSignal off
Interpolate on
}
Block {
BlockType Mux
Inputs "4"
DisplayOption "none"
UseBusObject off
BusObject "BusObject"
NonVirtualBus off
}
Block {
BlockType Outport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType PMComponent
SubClassName "unknown"
}
Block {
BlockType PMIOPort
}
Block {
BlockType Scope
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "-1"
}
Block {
BlockType Selector
InputType "Vector"
IndexMode "One-based"
ElementSrc "Internal"
Elements "1"
RowSrc "Internal"
Rows "1"
ColumnSrc "Internal"
Columns "1"
InputPortWidth "-1"
IndexIsStartValue off
OutputPortSize "1"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
Block {
BlockType Sin
SineType "Time based"
TimeSource "Use simulation time"
Amplitude "1"
Bias "0"
Frequency "1"
Phase "0"
Samples "10"
Offset "0"
SampleTime "-1"
VectorParams1D on
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
TreatAsAtomicUnit off
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Switch
Criteria "u2 >= Threshold"
Threshold "0"
InputSameDT on
OutDataTypeMode "Inherit via internal rule"
RndMeth "Floor"
SaturateOnIntegerOverflow on
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Terminator
}
Block {
BlockType ToWorkspace
VariableName "simulink_output"
MaxDataPoints "1000"
Decimation "1"
SampleTime "0"
FixptAsFi off
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Arial"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Arial"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "zhengliu"
Location [2, 82, 1014, 721]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "AC Voltage Source"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [93, 115, 117, 150]
Orientation "up"
SourceBlock "powerlib/Electrical\nSources/AC Voltage Source"
SourceType "AC Voltage Source"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Amplitude "220*sqrt(2)"
Phase "0"
Frequency "50"
SampleTime "0"
Measurements "Voltage"
}
Block {
BlockType Demux
Name "Demux"
Ports [1, 3]
Position [505, 306, 510, 414]
BackgroundColor "black"
ShowName off
Outputs "3"
DisplayOption "bar"
}
Block {
BlockType Reference
Name "Multimeter"
Ports [0, 1]
Position [415, 325, 480, 395]
SourceBlock "powerlib/Measurements/Multimeter"
SourceType "MultimeterPSB"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
PhasorSimulation off
OutputType "Complex"
sel "[2 3 1]"
L "3"
Gain "[1 1 1]"
yselected "{'Usrc: AC Voltage Source','Ib: Series RLC Bran"
"ch','Ub: Series RLC Branch'};"
PSBOutputType "1"
PSBequivalent "0"
AxesSetting "[0,0.1,-100,100]"
Display "0"
SavedBlockNames "-11"
}
Block {
BlockType Reference
Name "Neutral"
Ports [0, 0, 0, 0, 0, 1]
Position [95, 215, 115, 235]
Orientation "down"
ShowName off
AttributesFormatString "node %<NodeNumber>"
SourceBlock "powerlib/Elements/Neutral"
SourceType "Neutral"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "a"
NodeNumber "10"
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator"
Ports [0, 1]
Position [135, 258, 180, 292]
PulseType "Time based"
Period "0.02"
PulseWidth "2.5"
PhaseDelay "0.00167"
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator1"
Ports [0, 1]
Position [130, 333, 175, 367]
PulseType "Time based"
Period "0.02"
PulseWidth "2.5"
PhaseDelay "0.00167"
}
Block {
BlockType Scope
Name "Scope"
Ports [1]
Position [565, 309, 595, 341]
Floating off
Location [233, 156, 930, 391]
Open off
NumInputPorts "1"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
DataFormat "StructureWithTime"
SampleTime "0"
}
Block {
BlockType Scope
Name "Scope1"
Ports [2]
Position [580, 371, 610, 404]
Floating off
Location [5, 56, 1029, 741]
Open off
NumInputPorts "2"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
}
YMin "-5~-5"
YMax "5~5"
SaveName "ScopeData1"
DataFormat "StructureWithTime"
MaxDataPoints "50000"
SampleTime "0"
}
Block {
BlockType Scope
Name "Scope2"
Ports [2]
Position [280, 371, 310, 404]
Floating off
Location [-3, 56, 1021, 741]
Open off
NumInputPorts "2"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
}
YMin "0~-5"
YMax "1.5~5"
SaveName "ScopeData2"
DataFormat "StructureWithTime"
SampleTime "0"
}
Block {
BlockType Reference
Name "Series RLC Branch"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [571, 165, 599, 235]
Orientation "down"
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "R"
Resistance "2"
Inductance "1.0"
SetiL0 off
InitialCurrent "0"
Capacitance "1.0"
Setx0 off
InitialVoltage "0"
Measurements "Branch voltage and current"
}
Block {
BlockType Reference
Name "Voltage Measurement"
Ports [0, 1, 0, 0, 0, 2]
Position [850, 163, 875, 187]
NamePlacement "alternate"
SourceBlock "powerlib/Measurements/Voltage Measurement"
SourceType "Voltage Measurement"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
PhasorSimulation off
OutputType "Complex"
PSBequivalent "0"
}
Block {
BlockType Reference
Name "Vt1"
Ports [1, 1, 0, 0, 0, 1, 1]
Position [285, 25, 325, 80]
Orientation "up"
NamePlacement "alternate"
SourceBlock "powerlib/Power\nElectronics/Thyristor"
SourceType "Thyristor"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -