**title "TMS320VC5416's CPU memory-mapped registers"**/
********CPU Memory-Mapped Register*******************/
	IMR	.set  	00h		;;interrupt mask register*/
	IFR  	.set 	01h		;;interrupt flag register*/	
		 			;;02H-05H;reserved for register*/
	ST0  	.set 	06h		;;status register0*/		
	ST1  	.set 	07h		;;status register1*/
	AL	.set 	08H		;;accumulator A low word(15-0)*/
	AH	.set 	09H		;;accumulator A high word(31-16)*/
	AG 	.set 	0aH		;;accumulator A guard bits(39-32)*/
	BL	.set 	0bH		;;accumulator B low word(15-0)*/
	BH	.set 	0cH 		;;accumulator B high word(31-16)*/
	BG	.set 	0dH		;;accumulator B guard bits(39-32)*/
	TREG    .set 	0eH		;;temporary register*/
	TRN	.set 	0fH		;;transition register*/
	AR0	.set 	10H		;;auxiliary register0*/
	AR1	.set 	11H		;;auxiliary register1*/ 
	AR2	.set 	12H		;;auxiliary register2*/
	AR3	.set 	13H		;;auxiliary register3*/
	AR4	.set 	14H		;;auxiliary register4*/
	AR5	.set 	15H		;;auxiliary register5*/
	AR6	.set 	16H		;;auxiliary register6*/
	AR7	.set 	17H		;;auxiliary register7*/
	SP	.set 	18H		;;stack pointer register*/
	BK	.set 	19H		;;circular buffer size register*/
	BRC	.set 	1aH		;;block repeat counter8*/
	RSA	.set 	1bH		;;block repeat start address*/
	REA	.set 	1cH		;;block repeat end address*/
	PMST 	.set 	1dH		;;processor mode status(PMST) register*/
	XPC	.set 	1eH		;;extended program page register*/
		               		;;1fH 	;reserved*/
**********************************************************/
***Peripheral Memory-Mapped Register for Each DSP Subsystem*/
	DRR20 	.set 	20H		;;McBSP 0 Data Receive register 2
	DRR10 	.set 	21H		;;McBSP 0 Data Receive register 1
	DXR20 	.set 	22H		;;McBSP 0 Data Transmit register 2
	DXR10 	.set 	23H		;;McBSP 0 Data Transmit register 1
	TIM   	.set 	24H		;;Timer register
	PRD	.set 	25H		;;Timer period register
	TCR     .set 	26H		;;Timer control register
         				;;27H    ;Reserved
	SWWSR  	.set 	28H		;;Software wait-state register
	BSCR 	.set 	29H		;;Bank-switching control register
         			 	;;2aH	;Reserved
	SWCR  	.set	2bH		;;Software wait-state control register
	HPIC  	.set	2cH		;;HPI control register(HMODE=0 only)
					;;2dH-2fH;Reserved
	DRR22 	.set	30H		;;McBSP 2 Data Receive register 2
	DRR12 	.set	31H		;;McBSP 2 Data Receive register 1
	DXR22 	.set	32H		;;McBSP 2 Data Transmit register 2
	DXR12 	.set	33H		;;McBSP 2 Data Transmit register 1
	SPSA2 	.set	34H		;;McBSP 2 Subbank address register+
	SPSD2 	.set	35H		;;McBSP 2 subbank data register+
         				;;36h-37h;Reserved
	SPSA0 	.set	38H		;;McBSP 0 Subbank address registe+
	SPSD0 	.set	39H 		;;McBSP 0 subbank data register+
					;;3aH-3bH;Reserved
	GPIOCR 	.set	3cH		;;General-purpose I/O control registeer
	GPIOSR 	.set	3dH		;;General-purpose I/O status registeer
	CSIDR  	.set	3eH		;;Chip subsystem ID register
					;;3fH	;Reserved
	DRR21  	.set	40H		;;McBSP 1 Data Receive register 2
	DRR11  	.set	41H		;;McBSP 1 Data Receive register 1
	DXR21  	.set	42H		;;McBSP 1 Data Transmit register 2
	DXR11  	.set	43H		;;McBSP 1 Data Transmit register 1
					;;44H-47H;Reserved
	SPSA1  	.set	48H		;;McBSP 1 Subbank address registe+
	SPCD1  	.set	49H		;;McBSP 1 subbank data register+
					;;4aH-53H;Reserved
	DMPREC 	.set	54H		;;DMA priority and enable control register
	DMSA   	.set	55H		;;DMA Subbank address Register++
	DMSDI  	.set	56h 	   	;;DMA Subbank Data Register with autoincrement++
	DMSDN  	.set	57h 	    	;;DMA Subbank Data Register++ without modification
	CLKMD  	.set	58H		;;Clock mode register(CLKMD)