?? mcu.h
字號(hào):
#define PCNF2 (*(volatile unsigned char *)0xFA) /* PSC 2 Configuration Register */
#define PCTL2 (*(volatile unsigned char *)0xFB) /* PSC 2 Control Register */
#define PFRC2A (*(volatile unsigned char *)0xFC) /* PSC 2 Input A Control Register */
#define PFRC2B (*(volatile unsigned char *)0xFD) /* PSC 2 Input B Control Register */
#define PICR2 (*(volatile unsigned int *)0xFE) /* PSC 2 Input Capture Register */
/*==============================*/
/* Interrupt Vector Definitions */
/*==============================*/
#define RESET_vect 0
#define PSC2_CAPT_vect 1
#define PSC2EC_vect 2
#define PSC1_CAPT_vect 3
#define PSC1EC_vect 4
#define PSC0_CAPT_vect 5
#define PSC0EC_vect 6
#define ANACOMP_0_vect 7
#define ANACOMP_1_vect 8
#define ANACOMP_2_vect 9
#define INT0_vect 10
#define TIMER1_CAPT_vect 11
#define TIMER1_COMPA_vect 12
#define TIMER1_COMPB_vect 13
#define TIMER1_OVF_vect 15
#define TIMER0_COMPA_vect 16
#define TIMER0_OVF_vect 17
#define ADC_vect 18
#define INT1_vect 19
#define SPI_STC_vect 20
#define USART_RXC_vect 21
#define USART_UDRE_vect 22
#define USART_TXC_vect 23
#define INT2_vect 24
#define WDT_vect 25
#define EE_RDY_vect 26
#define TIMER0_COMPB_vect 27
#define INT3_vect 28
#define SPM_READY_vect 31
#endif /* _ICC_*/
/*==========================*/
/* Bit Position Definitions */
/*==========================*/
/* PINB : Input Pins, Port B */
#define PINB7 7
#define PINB6 6
#define PINB5 5
#define PINB4 4
#define PINB3 3
#define PINB2 2
#define PINB1 1
#define PINB0 0
/* DDRB : Data Direction Register, Port B */
#define DDB7 7
#define DDB6 6
#define DDB5 5
#define DDB4 4
#define DDB3 3
#define DDB2 2
#define DDB1 1
#define DDB0 0
/* PORTB : Data Register, Port B */
#define PB7 7
#define PB6 6
#define PB5 5
#define PB4 4
#define PB3 3
#define PB2 2
#define PB1 1
#define PB0 0
/* PORTB : Data Register, Port B */
#define PORTB7 7
#define PORTB6 6
#define PORTB5 5
#define PORTB4 4
#define PORTB3 3
#define PORTB2 2
#define PORTB1 1
#define PORTB0 0
/* PINC : Input Pins, Port C */
#define PINC7 7
#define PINC6 6
#define PINC5 5
#define PINC4 4
#define PINC3 3
#define PINC2 2
#define PINC1 1
#define PINC0 0
/* DDRC : Data Direction Register, Port C */
#define DDC7 7
#define DDC6 6
#define DDC5 5
#define DDC4 4
#define DDC3 3
#define DDC2 2
#define DDC1 1
#define DDC0 0
/* PORTC : Data Register, Port C */
#define PC7 7
#define PC6 6
#define PC5 5
#define PC4 4
#define PC3 3
#define PC2 2
#define PC1 1
#define PC0 0
/* PORTC : Data Register, Port C */
#define PORTC7 7
#define PORTC6 6
#define PORTC5 5
#define PORTC4 4
#define PORTC3 3
#define PORTC2 2
#define PORTC1 1
#define PORTC0 0
/* PIND : Input Pins, Port D */
#define PIND7 7
#define PIND6 6
#define PIND5 5
#define PIND4 4
#define PIND3 3
#define PIND2 2
#define PIND1 1
#define PIND0 0
/* DDRD : Data Direction Register, Port D */
#define DDD7 7
#define DDD6 6
#define DDD5 5
#define DDD4 4
#define DDD3 3
#define DDD2 2
#define DDD1 1
#define DDD0 0
/* PORTD : Data Register, Port D */
#define PD7 7
#define PD6 6
#define PD5 5
#define PD4 4
#define PD3 3
#define PD2 2
#define PD1 1
#define PD0 0
/* PORTD : Data Register, Port D */
#define PORTD7 7
#define PORTD6 6
#define PORTD5 5
#define PORTD4 4
#define PORTD3 3
#define PORTD2 2
#define PORTD1 1
#define PORTD0 0
/* PINE : Input Pins, Port E */
#define PINE7 7
#define PINE6 6
#define PINE5 5
#define PINE4 4
#define PINE3 3
#define PINE2 2
#define PINE1 1
#define PINE0 0
/* DDRE : Data Direction Register, Port E */
#define DDE7 7
#define DDE6 6
#define DDE5 5
#define DDE4 4
#define DDE3 3
#define DDE2 2
#define DDE1 1
#define DDE0 0
/* PORTE : Data Register, Port E */
#define PE7 7
#define PE6 6
#define PE5 5
#define PE4 4
#define PE3 3
#define PE2 2
#define PE1 1
#define PE0 0
/* PORTE : Data Register, Port E */
#define PORTE7 7
#define PORTE6 6
#define PORTE5 5
#define PORTE4 4
#define PORTE3 3
#define PORTE2 2
#define PORTE1 1
#define PORTE0 0
/* PINF : Input Pins, Port F */
#define PINF7 7
#define PINF6 6
#define PINF5 5
#define PINF4 4
#define PINF3 3
#define PINF2 2
#define PINF1 1
#define PINF0 0
/* TIFR0 : Timer/Counter Interrupt Flag Register 0 */
#define OCF0B 2
#define OCF0A 1
#define TOV0 0
/* TIFR1 : Timer/Counter Interrupt Flag Register 1 */
#define ICF1 5
#define OCF1B 2
#define OCF1A 1
#define TOV1 0
/* GPIOR1 */
#define GPIOR17 7
#define GPIOR16 6
#define GPIOR15 5
#define GPIOR14 4
#define GPIOR13 3
#define GPIOR12 2
#define GPIOR11 1
#define GPIOR10 0
/* GPIOR2 */
#define GPIOR27 7
#define GPIOR26 6
#define GPIOR25 5
#define GPIOR24 4
#define GPIOR23 3
#define GPIOR22 2
#define GPIOR21 1
#define GPIOR20 0
/* GPIOR3 */
#define GPIOR37 7
#define GPIOR36 6
#define GPIOR35 5
#define GPIOR34 4
#define GPIOR33 3
#define GPIOR32 2
#define GPIOR31 1
#define GPIOR30 0
/* EIFR : External Interrupt Flag Register */
#define INTF3 3
#define INTF2 2
#define INTF1 1
#define INTF0 0
/* EIMSK : External Interrupt Mask Register */
#define INT3 3
#define INT2 2
#define INT1 1
#define INT0 0
/* GPIOR0 */
#define GPIOR07 7
#define GPIOR06 6
#define GPIOR05 5
#define GPIOR04 4
#define GPIOR03 3
#define GPIOR02 2
#define GPIOR01 1
#define GPIOR00 0
/* EECR : EEPROM Control Register */
#define EERIE 3
#define EEMWE 2
#define EEWE 1
#define EERE 0
/* GTCCR : General Timer Control Register */
#define TSM 7
#define ICPSEL1 6
#define PSRSYNC 0
/* TCCR0A : Timer/Counter 0 Control Register A */
#define COM0A1 7
#define COM0A0 6
#define COM0B1 5
#define COM0B0 4
#define WGM01 1
#define WGM00 0
/* TCCR0B : Timer/Counter 0 Control Register B */
#define FOC0A 7
#define FOC0B 6
#define WGM02 3
#define CS02 2
#define CS01 1
#define CS00 0
/* PLLCSR */
#define PLLF 2
#define PLLE 1
#define PLLOCK 0
#define PLOCK 0
/* SPCR : SPI Control Register */
#define SPIE 7
#define SPE 6
#define DORD 5
#define MSTR 4
#define CPOL 3
#define CPHA 2
#define SPR1 1
#define SPR0 0
/* SPSR : SPI Status Register */
#define SPIF 7
#define WCOL 6
#define SPI2X 0
/* ACSR : Analog Comparator Control and Status Register */
#define ACCKDIV 7
#define AC2IF 6
#define AC1IF 5
#define AC0IF 4
#define AC2O 2
#define AC1O 1
#define AC0O 0
/* SMCR : Sleep Mode Control Register */
#define SM2 3
#define SM1 2
#define SM0 1
#define SE 0
/* MCUSR : MCU general Status Register */
#define WDRF 3
#define BORF 2
#define EXTRF 1
#define PORF 0
/* MCUCR : MCU general Control Register */
#define SPIPS 7
#define PUD 4
#define IVSEL 1
#define IVCE 0
/* SPMCR : Store Program Memory Control and Status Register */
#define SPMIE 7
#define RWWSB 6
#define RWWSRE 4
#define BLBSET 3
#define PGWRT 2
#define PGERS 1
#define SPMEN 0
/* SPH : Stack Pointer High */
#define SP15 7
#define SP14 6
#define SP13 5
#define SP12 4
#define SP11 3
#define SP10 2
#define SP9 1
#define SP8 0
/* SPL : Stack Pointer Low */
#define SP7 7
#define SP6 6
#define SP5 5
#define SP4 4
#define SP3 3
#define SP2 2
#define SP1 1
#define SP0 0
/* WTDCSR : Watchdog Timer Control Register */
#define WDIF 7
#define WDIE 6
#define WDP3 5
#define WDCE 4
#define WDE 3
#define WDP2 2
#define WDP1 1
#define WDP0 0
/* CLKPR : Source Clock Prescaler Register */
#define CKLPCE 7
#define CKLPS3 3
#define CKLPS2 2
#define CKLPS1 1
#define CKLPS0 0
/* PRR */
#define PRPSC2 7
#define PRPSC1 6
#define PRPSC0 5
#define PRTIM1 4
#define PRTIM0 3
#define PRSPI 2
#define PRUSART 1
#define PRADC 0
/* OSCAL */
#define CAL6 6
#define CAL5 5
#define CAL4 4
#define CAL3 3
#define CAL2 2
#define CAL1 1
#define CAL0 0
/* EICRA */
#define ISC31 7
#define ISC30 6
#define ISC21 5
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