#define    ISC20     4
#define    ISC11     3
#define    ISC10     2
#define    ISC01     1
#define    ISC00     0

/* TIMSK0 : Timer Interrupt Mask Register0 */
#define    OCIE0B    2
#define    OCIE0A    1
#define    TOIE0     0

/* TIMSK1 : Timer Interrupt Mask Register1 */
#define    ICIE1     5
#define    OCIE1B    2
#define    OCIE1A    1
#define    TOIE1     0

/* AMP0CSR  */
#define    AMP0EN    7
#define    AMP0IS    6
#define    AMP0G1    5
#define    AMP0G0    4
#define    AMP0TS2   2
#define    AMP0TS1   1
#define    AMP0TS0   0

/* AMP1CSR  */
#define    AMP1EN    7
#define    AMP1IS    6
#define    AMP1G1    5
#define    AMP1G0    4
#define    AMP1TS2   2
#define    AMP1TS1   1
#define    AMP1TS0   0

/* ADCSRA : ADC Control and Status Register A*/
#define    ADEN      7
#define    ADSC      6
#define    ADATE     5
#define    ADIF      4
#define    ADIE      3
#define    ADPS2     2
#define    ADPS1     1
#define    ADPS0     0

/* ADCSRB : ADC Control and Status Register B*/
#define    ADHSM     7
#define    ADASCR    4
#define    ADST3     3
#define    ADST2     2
#define    ADST1     1
#define    ADST0     0

/* ADMUX : ADC Multiplexer Selection Register */
#define    REFS1     7
#define    REFS0     6
#define    ADLAR     5
#define    MUX3      3
#define    MUX2      2
#define    MUX1      1
#define    MUX0      0

/* DIDR0 */
#define    ADC7D     7
#define    ADC6D     6
#define    ADC5D     5
#define    ADC4D     4
#define    ADC3D     3
#define    ADC2D     2
#define    ADC1D     1
#define    ADC0D     0

/* DIDR1 */
#define    ACMP0D    5
#define    AMP0PD    4
#define    AMP0ND    3
#define    ADC10D    2
#define    ACMP1D    2
#define    ADC9D     1
#define    AMP1PD    1
#define    ADC8D     0
#define    AMP1ND    0

/* TCCR1A : Timer/Counter 1 Control Register A */
#define    COM1A1    7
#define    COM1A0    6
#define    COM1B1    5
#define    COM1B0    4
#define    WGM11     1
#define    WGM10     0

/* TCCR1B : Timer/Counter 1 Control Register B */
#define    ICNC1     7
#define    ICES1     6
#define    WGM13     4
#define    WGM12     3
#define    CS12      2
#define    CS11      1
#define    CS10      0

/* TCCR1C : Timer/Counter 1 Control Register C */
#define    FOC1A     7
#define    FOC1B     6

/* PIFR0 : PSC 0 Interrupt Flag Register */
#define    PSEI0     5
#define    PEV0B     4
#define    PEV0A     3
#define    PRN01     2
#define    PRN00     1
#define    PEOP0     0

/* PIM0 : PSC 0 Interrupt Mask Register */
#define    PSEIE0    5
#define    PEVE0B    4
#define    PEVE0A    3
#define    PEOPE0    0

/* PIFR1 : PSC 1 Interrupt Flag Register */
#define    PSEI1     5
#define    PEV1B     4
#define    PEV1A     3
#define    PRN11     2
#define    PRN10     1
#define    PEOP1     0

/* PIM1 : PSC 1 Interrupt Mask Register */
#define    PSEIE1    5
#define    PEVE1B    4
#define    PEVE1A    3
#define    PEOPE1    0

/* PIFR2 : PSC 2 Interrupt Flag Register */
#define    PSEI2     5
#define    PEV2B     4
#define    PEV2A     3
#define    PRN21     2
#define    PRN20     1
#define    PEOP2     0

/* PIM2 : PSC 2 Interrupt Mask Register */
#define    PSEIE1    5
#define    PEVE2B    4
#define    PEVE2A    3
#define    PEOPE2    0

/* DACON: DAC Control and Status Register */
#define    DAATE     7
#define    DATS2     6
#define    DATS1     5
#define    DATS0     4
#define    DALA      2
#define    DAOE      1
#define    DAEN      0

/* AC0CON : Analog comparator 0 Control and Status Register */
#define    AC0EN     7
#define    AC0IE     6
#define    AC0IS1    5
#define    AC0IS0    4
#define    AC0M2     2
#define    AC0M1     1
#define    AC0M0     0

/* AC1CON : Analog comparator 1 Control and Status Register */
#define    AC1EN     7
#define    AC1IE     6
#define    AC1IS1    5
#define    AC1IS0    4
#define    AC1ICE    3
#define    AC1M2     2
#define    AC1M1     1
#define    AC1M0     0

/* AC2CON : Analog comparator 2 Control and Status Register */
#define    AC2EN     7
#define    AC2IE     6
#define    AC2IS1    5
#define    AC2IS0    4
#define    AC2SADE   3
#define    AC2M2     2
#define    AC2M1     1
#define    AC2M0     0

/* UCSRA : USART Control and Status Register A */
#define    RXC       7
#define    TXC       6
#define    UDRE      5
#define    FE        4
#define    DOR       3
#define    UPE       2
#define    U2X       1
#define    MPCM      0

/* UCSRB : USART Control and Status Register B */
#define    RXCIE     7
#define    TXCIE     6
#define    UDRIE     5
#define    RXEN      4
#define    TXEN      3
#define    UCSZ2     2
#define    RXB8      1
#define    TXB8      0

/* UCSRC : USART Control and Status Register C */
#define    UMSEL     6
#define    UPM1      5
#define    UPM0      4
#define    USBS      3
#define    UCSZ1     2
#define    UCSZ0     1
#define    UCPOL     0

/* USART0 left for compatiblity reason */
/* UCSR0A : USART0 Control and Status Register A */
#define    RXC0      7
#define    TXC0      6
#define    UDRE0     5
#define    FE0       4
#define    DOR0      3
#define    UPE0      2
#define    U2X0      1
#define    MPCM0     0

/* UCSR0B : USART0 Control and Status Register B */
#define    RXCIE0    7
#define    TXCIE0    6
#define    UDRIE0    5
#define    RXEN0     4
#define    TXEN0     3
#define    UCSZ02    2
#define    RXB80     1
#define    TXB80     0

/* UCSR0C : USART0 Control and Status Register C */
#define    UMSEL0    6
#define    UPM01     5
#define    UPM00     4
#define    USBS0     3
#define    UCSZ01    2
#define    UCSZ00    1
#define    UCPOL0    0

/* EUSART */
/* EUCSRA : EUSART Control and Status Register A */
#define    UTxS3     7
#define    UTxS2     6
#define    UTxS1     5
#define    UTxS0     4
#define    URxS3     3
#define    URxS2     2
#define    URxS1     1
#define    URxS0     0

/* EUCSRB : EUSART Control and Status Register B */
#define    EUSART    4
#define    EUSBS     3
#define    EMCH      1
#define    BODR      0

/* EUCSRC : EUSART Control and Status Register C */
#define    FEM       3
#define    F1617     2
#define    STP1      1
#define    STP0      0

/* PSOC0 : PSC 0 Synchro and Output Configuration */
#define    PSYNC01   5
#define    PSYNC00   4
#define    POEN0B    2
#define    POEN0A    0

/* PCNF0 : PSC 0 Configuration */
#define    PFIFTY0   7
#define    PALOCK0   6
#define    PLOCK0    5
#define    PMODE01   4
#define    PMODE00   3
#define    POP0      2
#define    PCLKSEL0  1

/* PCTL0 : PSC 0 Control */
#define    PPRE01    7
#define    PPRE00    6
#define    PBFM0     5
#define    PAOC0B    4
#define    PAOC0A    3
#define    PARUN0    2
#define    PCCYC0    1
#define    PRUN0     0

/* PFRC0A : PSC 0 Input A Control Register */
#define    PCAPE0A   7
#define    PISEL0A   6
#define    PELEV0A   5
#define    PFLTE0A   4
#define    PRFM0A3   3
#define    PRFM0A2   2
#define    PRFM0A1   1
#define    PRFM0A0   0

/* PFRC0B : PSC 0 Input B Control Register */
#define    PCAPE0B   7
#define    PISEL0B   6
#define    PELEV0B   5
#define    PFLTE0B   4
#define    PRFM0B3   3
#define    PRFM0B2   2
#define    PRFM0B1   1
#define    PRFM0B0   0

/* PSOC1 : PSC 1 Synchro and Output Configuration */
#define    PSYNC11   5
#define    PSYNC10   4
#define    POEN1B    2
#define    POEN1A    0

/* PCNF1 : PSC 1 Configuration */
#define    PFIFTY1   7
#define    PALOCK1   6
#define    PLOCK1    5
#define    PMODE11   4
#define    PMODE10   3
#define    POP1      2
#define    PCLKSEL1  1

/* PCTL1 : PSC 1 Control */
#define    PPRE11    7
#define    PPRE10    6
#define    PBFM1     5
#define    PAOC1B    4
#define    PAOC1A    3
#define    PARUN1    2
#define    PCCYC1    1
#define    PRUN1     0

/* PFRC1A : PSC 1 Input A Control Register */
#define    PCAPE1A   7
#define    PISEL1A   6
#define    PELEV1A   5
#define    PFLTE1A   4
#define    PRFM1A3   3
#define    PRFM1A2   2
#define    PRFM1A1   1
#define    PRFM1A0   0

/* PFRC1B : PSC 1 Input B Control Register */
#define    PCAPE1B   7
#define    PISEL1B   6
#define    PELEV1B   5
#define    PFLTE1B   4
#define    PRFM1B3   3
#define    PRFM1B2   2
#define    PRFM1B1   1
#define    PRFM1B0   0

/* PSOC2 : PSC 2 Synchro and Output Configuration */
#define    POS23     7
#define    POS22     6
#define    PSYNC21   5
#define    PSYNC20   4
#define    POEN2D    3
#define    POEN2B    2
#define    POEN2C    1
#define    POEN2A    0

/* POM2 : PSC 2 Output Matrix */
#define    POMV2B3   7
#define    POMV2B2   6
#define    POMV2B1   5
#define    POMV2B0   4
#define    POMV2A3   3
#define    POMV2A2   2
#define    POMV2A1   1
#define    POMV2A0   0

/* PCNF2 : PSC 2 Configuration */
#define    PFIFTY2   7
#define    PALOCK2   6
#define    PLOCK2    5
#define    PMODE21   4
#define    PMODE20   3
#define    POP2      2
#define    PCLKSEL2  1
#define    POME2     0

/* PCTL2 : PSC 2 Control */
#define    PPRE21    7
#define    PPRE20    6
#define    PBFM2     5
#define    PAOC2B    4
#define    PAOC2A    3
#define    PARUN2    2
#define    PCCYC2    1
#define    PRUN2     0

/* PFRC2A : PSC 2 Input A Control Register */
#define    PCAPE2A   7
#define    PISEL2A   6
#define    PELEV2A   5
#define    PFLTE2A   4
#define    PRFM2A3   3
#define    PRFM2A2   2
#define    PRFM2A1   1
#define    PRFM2A0   0

/* PFRC2B : PSC 2 Input B Control Register */
#define    PCAPE2B   7
#define    PISEL2B   6
#define    PELEV2B   5
#define    PFLTE2B   4
#define    PRFM2B3   3
#define    PRFM2B2   2
#define    PRFM2B1   1
#define    PRFM2B0   0

/* Pointer definition */
#define    XL     r26
#define    XH     r27
#define    YL     r28
#define    YH     r29
#define    ZL     r30
#define    ZH     r31

#endif  /* _MCU_H*/