?? spmc75_regs.h
字號:
typedef union
{
UInt16 W;
struct
{
UInt16 DTP : 7;
UInt16 Reserved1 : 5;
UInt16 DTUE : 1;
UInt16 DTVE : 1;
UInt16 DTWE : 1;
UInt16 Reserved2 : 1;
} B;
} P_TMR4_DeadTime_DEF;
/*****************************************************************************/
/* Timer/PWM Module Write Enable Control Register(P_TPWM_Write) */
/* Bit 0 : TMR3WE, Timer 3 setting registers write enable select */
/* Bit 1 : TMR4WE, Timer 4 setting registers write enable select */
/* Bit 15 - 2 : Reserve */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 TMR3WE : 1;
UInt16 TMR4WE : 1;
UInt16 Reserved : 14;
} B;
} P_TPWM_Write_DEF;
/*****************************************************************************/
/* Fault Input 1/2 Control and Status Register(P_Fault1/2_Ctrl) */
/* Bit 3 - 0 : FTCNT, Fault protection sampling time */
/* Bit 4 : Reserve */
/* Bit 5 : FTPINIF, Fault input 1/2 status flag */
/* Bit 6 : FTPINIE, Fault input 1/2 interrupt enable */
/* Bit 7 : FTPINE, Fault input pin 1/2 enable */
/* Bit 11 - 8 : Reserve */
/* Bit 12 : OSF, Output short flag */
/* Bit 13 : OCLS, Output compare polarity level select */
/* Bit 14: : OCIE, Output compare interrupt enable */
/* Bit 15: : OCE, Output compare enable */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 FTCNT : 4;
UInt16 Reserved1 : 1;
UInt16 FTPINIF : 1;
UInt16 FTPINIE : 1;
UInt16 FTPINE : 1;
UInt16 Reserved2 : 4;
UInt16 OSF : 1;
UInt16 OCLS : 1;
UInt16 OCIE : 1;
UInt16 OCE : 1;
} B;
} P_Fault1_Ctrl_DEF;
typedef union
{
UInt16 W;
struct
{
UInt16 FTCNT : 4;
UInt16 Reserved1 : 1;
UInt16 FTPINIF : 1;
UInt16 FTPINIE : 1;
UInt16 FTPINE : 1;
UInt16 Reserved2 : 4;
UInt16 OSF : 1;
UInt16 OCLS : 1;
UInt16 OCIE : 1;
UInt16 OCE : 1;
} B;
} P_Fault2_Ctrl_DEF;
/*****************************************************************************/
/* Overload Protection 1/2 Control/Status Register (P_OL1/2_Ctrl) */
/* (P_TMR3/4_OLProtect) */
/* Bit 3 - 0 : OLCNT, Overload protection sampling time */
/* Bit 5 - 4 : Reserve */
/* Bit 6 : OLIF, Overload interrupt flag */
/* Bit 7 : OLIE, Overload interrupt enable bit */
/* Bit 8 : RTOL, Return from overload protection state */
/* Bit 9 : RTPWM, Return from PWM sync enable bit */
/* Bit 10 : RTTMB, Return from P_TMR0/1_TGRB register compare match */
/* interrupt enable bit */
/* Bit 11 : OLST, Overload protection status */
/* Bit 12:13 : OLMD, Output disabled phases during overload protection */
/* Bit 14: : CNTSP,Stop PWM counter during overload protection select */
/* Bit 15: : OLEN, Overload protection enable */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 OLCNT : 4;
UInt16 Reserved : 2;
UInt16 OLIF : 1;
UInt16 OLIE : 1;
UInt16 RTOL : 1;
UInt16 RTPWM : 1;
UInt16 RTTMB : 1;
UInt16 OLST : 1;
UInt16 OLMD : 2;
UInt16 CNTSP : 1;
UInt16 OLEN : 1;
} B;
} P_OL1_Ctrl_DEF;
typedef union
{
UInt16 W;
struct
{
UInt16 OLCNT : 4;
UInt16 Reserved : 2;
UInt16 OLIF : 1;
UInt16 OLIE : 1;
UInt16 RTOL : 1;
UInt16 RTPWM : 1;
UInt16 RTTMB : 1;
UInt16 OLST : 1;
UInt16 OLMD : 2;
UInt16 CNTSP : 1;
UInt16 OLEN : 1;
} B;
} P_OL2_Ctrl_DEF;
/*****************************************************************************/
/* Fault 1/2 Flag Release Register(P_Fault1/2_Release) */
/* bit 0 - 15 : FTRR */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 FTRR : 16;
} B;
} P_Fault1_Release_DEF;
typedef union
{
UInt16 W;
struct
{
UInt16 FTRR : 16;
} B;
} P_Fault2_Release_DEF;
/*****************************************************************************/
/*****************************************************************************/
/* L. 10-bit ADC converter register */
/*****************************************************************************/
/*****************************************************************************/
/* ADC Setup register (P_ADC_Setup) */
/* bit 6:0 :Reserve */
/* bit 7 :ASPEN, Auto Sampling mode enable */
/* bit 8 :ADCEXTRG, external ADC conversion request trigger from PB8 pad */
/* bit 10:9 :ADCFS, A/D converter clock selection */
/* =00: CPUCLK /8 */
/* =01: CPUCLK /16 */
/* =10: CPUCLK /32 */
/* =11: CPUCLK /64 */
/* bit 11 :Reserve */
/* bit 12 :Reserve */
/* bit 13 :Reserve */
/* bit 14 :ADCEN, ADC converter enable */
/* bit 15 :ADCCS, ADC converter chip select. (ADC Power on) */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 Reserved1 : 7;
UInt16 ASPEN : 1;
UInt16 ADCEXTRG : 1;
UInt16 ADCFS : 2;
UInt16 Reserved2 : 3;
UInt16 ADCEN : 1;
UInt16 ADCCS : 1;
} B;
} P_ADC_Setup_DEF;
/*****************************************************************************/
/* ADC control register (P_ADC_Ctrl) */
/* bit 2:0 :ADCCHS, Select ADC converter channel input */
/* =000: ADC Channel 0 (PA0) */
/* =001: ADC Channel 1 (PA1) */
/* =010: ADC Channel 2 (PA2) */
/* =011: ADC Channel 3 (PA3) */
/* =100: ADC Channel 4 (PA4) */
/* =101: ADC Channel 5 (PA5) */
/* =110: ADC Channel 6 (PA6) */
/* =111: ADC Channel 7 (PA7) */
/* bit 5:3 :Reserve */
/* bit 6 :ADCSTR, Manual Start ADC Conversion */
/* bit 7 :ADCRDY, ADC conversion ready */
/* bit 13: 8 :Reserved */
/* bit 14 :ADCIE, ADC interrupt enable */
/* bit 15 :ADCIF, ADC interrupt flag */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 ADCCHS : 3;
UInt16 Reserved1 : 3;
UInt16 ADCSTR : 1;
UInt16 ADCRDY : 1;
UInt16 Reserved2 : 6;
UInt16 ADCIE : 1;
UInt16 ADCIF : 1;
} B;
} P_ADC_Ctrl_DEF;
/*****************************************************************************/
/* ADC Input Channels Select (P_ADC_Channel) */
/* bit 0 :ADCCH0, ADC Input Channel0 Enable */
/* bit 1 :ADCCH1, ADC Input Channel1 Enable
/* bit 2 :ADCCH2, ADC Input Channel2 Enable */
/* bit 3 :ADCCH3, ADC Input Channel3 Enable
/* bit 4 :ADCCH4, ADC Input Channel4 Enable */
/* bit 5 :ADCCH5, ADC Input Channel5 Enable
/* bit 6 :ADCCH6, ADC Input Channel6 Enable */
/* bit 7 :ADCCH7, ADC Input Channel7 Enable
/* bit 8:15 :Reserve
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 ADCCH0 : 1;
UInt16 ADCCH1 : 1;
UInt16 ADCCH2 : 1;
UInt16 ADCCH3 : 1;
UInt16 ADCCH4 : 1;
UInt16 ADCCH5 : 1;
UInt16 ADCCH6 : 1;
UInt16 ADCCH7 : 1;
UInt16 reserved : 8;
} B;
} P_ADC_Channel_DEF;
/*****************************************************************************/
/* ADC Data Register (P_ADC_Data) */
/* bit 5 - 0 : reserved */
/* bit 15 - 6 : ADCData, ADC conversion data */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 reserved : 6;
UInt16 ADCData : 10;
} B;
} P_ADC_Data_DEF;
/*****************************************************************************/
/*****************************************************************************/
/* H. Standard Peripheral Interface, SPI register */
/*****************************************************************************/
/*****************************************************************************/
/* SPI control register (P_SPI_Ctrl) */
/* bit 2:0 :SPIFS, Master mode clock frequency selection */
/* bit 3 :SPISMPS, SPI sample mode selection for master mode */
/* bit 4 :SPIPOL, SPI clock polarity. SPI clock polarity select */
/* bit 5 :SPIPHA, SPI clock phase */
/* bit 7:6 :Reserve */
/* bit 8 :SPIMS, SPI mode selection */
/* bit 10:9 :SPISPCLK, Sampling clock select bits */
/* bit 11 :SPIRST, Write 1 to reset */
/* bit 14:12:Reserve */
/* bit 15 :SPIE, SPI enable */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 SPIFS : 3;
UInt16 SPISMPS : 1;
UInt16 SPIPOL : 1;
UInt16 SPIPHA : 1;
UInt16 Reserved1 : 2;
UInt16 SPIMS : 1;
UInt16 SPISPCLK : 2;
UInt16 SPIRST : 1;
UInt16 Reserved2 : 3;
UInt16 SPIE : 1;
} B;
} P_SPI_Ctrl_DEF;
/*****************************************************************************/
/* SPI Tx status register (P_SPI_TxStatus) */
/* bit 12:0 :Reserve */
/* bit 13 :SPITXBF, SPI Transmission buffer full flag. */
/* bit 14 :SPITXIE, SPI Transmit interrupt enable */
/* bit 15 :SPITXIF, SPI Transmit interrupt flag */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 Reserved : 13;
UInt16 SPITXBF : 1;
UInt16 SPITXIE : 1;
UInt16 SPITXIF : 1;
} B;
} P_SPI_TxStatus_DEF;
/*****************************************************************************/
/* SPI Transmission Buffer (P_SPI_TxBuf) */
/* bit 7 - 0 : SPITXBUF,Write data sends to SDO pin */
/* bit 15- 8 : Reserve */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 SPITXBUF : 8;
UInt16 reserved : 8;
} B;
} P_SPI_TxBuf_DEF;
/*****************************************************************************/
/* SPI Rx status register (P_SPI_RxStatus) */
/* bit 9:0 :Reserve */
/* bit 10 :FERR, Buffer full and overwrite */
/* bit 13:11:Reserve */
/* bit 14 :SPIRXIE, SPI receive interrupt enable */
/* bit 15 :SPIRXIF, SPI receive interrupt flag */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 Reserved1 : 10;
UInt16 FERR : 1;
UInt16 Reserved2 : 3;
UInt16 SPIRXIE : 1;
UInt16 SPIRXIF : 1;
} B;
} P_SPI_RxStatus_DEF;
/*****************************************************************************/
/* SPI Receive Buffer (P_SPI_RxBuf) */
/* bit 7 - 0 : SPIRXBUF,Read data from SDI pin */
/* bit 15- 8 : Reserve */
/*****************************************************************************/
typedef union
{
UInt16 W;
struct
{
UInt16 SPIRXBUF : 8;
UInt16 reserved : 8;
} B;
} P_SPI_RxBuf_DEF;
/*****************************************************************************/
/* Reset status register (P_Reset_Status) */
/* bit 0 : EXTRF, External reset pin reset flag */
/* bit 1 : PORF, Power-on reset flag */
/* bit 2 : WDRF, Watchdog reset flag */
/* bit 3 : LPLVRF, Long period low voltage reset flag */
/* bit 4 : SPLVRF, Short period low voltage reset flag */
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