/* ========================================================================= */
/* File Name   : Spmc75f_debug.c										     */	
/* Project     : SPMC75F2413A chip verification							     */
/* Description : regitser debugging mode for SPMC75F series				     */
/* Processor   : SPMC75F series											     */	
/* Author      : Chih ming Huang										     */
/* Date        : May 2004												     */
/* Tools	   : u'nSP IDE tools v1.14.1								     */
/* Version     : 1.00 													     */	
/* Security    : Confidential Proprietary 							         */
/* E-Mail      : MaxHuang@sunplus.com.tw								     */
/* ========================================================================= */
#include "Spmc75_regs.h"

#ifdef SPMC751_REG_DEBUG
	/* A. CPU control register */
	P_System_Option_DEF		*P_System_Option = (P_System_Option_DEF *)P_System_Option_ADDR;
	P_Wait_Enter_DEF		*P_Wait_Enter    = (P_Wait_Enter_DEF *)P_Wait_Enter_ADDR;	
	P_Stdby_Enter_DEF		*P_Stdby_Enter   = (P_Stdby_Enter_DEF *)P_Stdby_Enter_ADDR;
	P_Reset_Status_DEF		*P_Reset_Status  = (P_Reset_Status_DEF *)P_Reset_Status_ADDR;	
	P_Clk_Ctrl_DEF			*P_Clk_Ctrl      = (P_Clk_Ctrl_DEF *)P_Clk_Ctrl_ADDR;
	
	P_WatchDog_Ctrl_DEF		*P_WatchDog_Ctrl = (P_WatchDog_Ctrl_DEF *)P_WatchDog_Ctrl_ADDR; 
	P_WatchDog_Clr_DEF		*P_WatchDog_Clr  = (P_WatchDog_Clr_DEF *)P_WatchDog_Clr_ADDR;	
	P_INT_Status_DEF		*P_INT_Status    = (P_INT_Status_DEF *)P_INT_Status_ADDR;
	P_INT_Priority_DEF		*P_INT_Priority  = (P_INT_Priority_DEF *)P_INT_Priority_ADDR;
	P_MisINT_Ctrl_DEF		*P_MisINT_Ctrl   = (P_MisINT_Ctrl_DEF *)P_MisINT_Ctrl_ADDR;
	
	/* B. I/O Ports */
	/* B1. PortA register*/
	GEN_REG_DEF				*P_IOA_Data   = (GEN_REG_DEF *)P_IOA_Data_ADDR;
	GEN_REG_DEF				*P_IOA_Buffer = (GEN_REG_DEF *)P_IOA_Buffer_ADDR;
	GEN_REG_DEF				*P_IOA_Dir    = (GEN_REG_DEF *)P_IOA_Dir_ADDR;
	GEN_REG_DEF				*P_IOA_Attrib = (GEN_REG_DEF *)P_IOA_Attrib_ADDR;
	GEN_REG_DEF				*P_IOA_Latch  = (GEN_REG_DEF *)P_IOA_Latch_ADDR;
	P_IOA_SPE_DEF			*P_IOA_SPE	  = (P_IOA_SPE_DEF *)P_IOA_SPE_ADDR;
	P_IOA_KCER_DEF			*P_IOA_KCER	  = (P_IOA_KCER_DEF *)P_IOA_KCER_ADDR;			
	
	/* B2. PortB register*/
	GEN_REG_DEF				*P_IOB_Data   = (GEN_REG_DEF *)P_IOB_Data_ADDR;
	GEN_REG_DEF				*P_IOB_Buffer = (GEN_REG_DEF *)P_IOB_Buffer_ADDR;
	GEN_REG_DEF				*P_IOB_Dir    = (GEN_REG_DEF *)P_IOB_Dir_ADDR;
	GEN_REG_DEF				*P_IOB_Attrib = (GEN_REG_DEF *)P_IOB_Attrib_ADDR;
	GEN_REG_DEF				*P_IOB_Latch  = (GEN_REG_DEF *)P_IOB_Latch_ADDR;
	P_IOB_SPE_DEF			*P_IOB_SPE	  = (P_IOB_SPE_DEF *)P_IOB_SPE_ADDR;

	/* B3. PortC register*/
	GEN_REG_DEF				*P_IOC_Data   = (GEN_REG_DEF *)P_IOC_Data_ADDR;
	GEN_REG_DEF				*P_IOC_Buffer = (GEN_REG_DEF *)P_IOC_Buffer_ADDR;
	GEN_REG_DEF				*P_IOC_Dir    = (GEN_REG_DEF *)P_IOC_Dir_ADDR;
	GEN_REG_DEF				*P_IOC_Attrib = (GEN_REG_DEF *)P_IOC_Attrib_ADDR;
	GEN_REG_DEF				*P_IOC_Latch  = (GEN_REG_DEF *)P_IOC_Latch_ADDR;
	P_IOC_SPE_DEF			*P_IOC_SPE	  = (P_IOC_SPE_DEF *)P_IOC_SPE_ADDR;

	/* B4. PortD register*/
	GEN_REG_DEF				*P_IOD_Data   = (GEN_REG_DEF *)P_IOD_Data_ADDR;
	GEN_REG_DEF				*P_IOD_Buffer = (GEN_REG_DEF *)P_IOD_Buffer_ADDR;
	GEN_REG_DEF				*P_IOD_Dir    = (GEN_REG_DEF *)P_IOD_Dir_ADDR;
	GEN_REG_DEF				*P_IOD_Attrib = (GEN_REG_DEF *)P_IOD_Attrib_ADDR;
	GEN_REG_DEF				*P_IOD_Latch  = (GEN_REG_DEF *)P_IOD_Latch_ADDR;

	/* C. Temer  */
	/* C1. Timer0 register */
	P_TMR0_1_2_Ctrl_DEF		*P_TMR0_Ctrl = (P_TMR0_1_2_Ctrl_DEF *)P_TMR0_Ctrl_ADDR;
	GEN_REG_DEF				*P_TMR0_TCNT = (GEN_REG_DEF *)P_TMR0_TCNT_ADDR;
	GEN_REG_DEF				*P_TMR0_TGRA = (GEN_REG_DEF *)P_TMR0_TGRA_ADDR;
	GEN_REG_DEF				*P_TMR0_TGRB = (GEN_REG_DEF *)P_TMR0_TGRB_ADDR;
	GEN_REG_DEF				*P_TMR0_TGRC = (GEN_REG_DEF *)P_TMR0_TGRC_ADDR;
	GEN_REG_DEF				*P_TMR0_TPR  = (GEN_REG_DEF *)P_TMR0_TPR_ADDR;
	GEN_REG_DEF				*P_TMR0_TBRA = (GEN_REG_DEF *)P_TMR0_TBRA_ADDR;
	GEN_REG_DEF				*P_TMR0_TBRB = (GEN_REG_DEF *)P_TMR0_TBRB_ADDR;
	GEN_REG_DEF				*P_TMR0_TBRC = (GEN_REG_DEF *)P_TMR0_TBRC_ADDR;
	P_TMR0_1_IOCtrl_DEF		*P_TMR0_IOCtrl = (P_TMR0_1_IOCtrl_DEF *)P_TMR0_IOCtrl_ADDR; 
	P_TMR0_1_INT_DEF		*P_TMR0_INT    = (P_TMR0_1_INT_DEF *)P_TMR0_INT_ADDR;
	P_TMR0_1_Status_DEF		*P_TMR0_Status = (P_TMR0_1_Status_DEF *)P_TMR0_Status_ADDR;				

	/* C2. Timer1 register */
	P_TMR0_1_2_Ctrl_DEF		*P_TMR1_Ctrl = (P_TMR0_1_2_Ctrl_DEF *)P_TMR1_Ctrl_ADDR;;
	GEN_REG_DEF				*P_TMR1_TCNT = (GEN_REG_DEF *)P_TMR1_TCNT_ADDR;
	GEN_REG_DEF				*P_TMR1_TGRA = (GEN_REG_DEF *)P_TMR1_TGRA_ADDR;
	GEN_REG_DEF				*P_TMR1_TGRB = (GEN_REG_DEF *)P_TMR1_TGRB_ADDR;
	GEN_REG_DEF				*P_TMR1_TGRC = (GEN_REG_DEF *)P_TMR1_TGRC_ADDR;
	GEN_REG_DEF				*P_TMR1_TPR  = (GEN_REG_DEF *)P_TMR1_TPR_ADDR;
	GEN_REG_DEF				*P_TMR1_TBRA = (GEN_REG_DEF *)P_TMR1_TBRA_ADDR;
	GEN_REG_DEF				*P_TMR1_TBRB = (GEN_REG_DEF *)P_TMR1_TBRB_ADDR;
	GEN_REG_DEF				*P_TMR1_TBRC = (GEN_REG_DEF *)P_TMR1_TBRC_ADDR;
	P_TMR0_1_IOCtrl_DEF		*P_TMR1_IOCtrl = (P_TMR0_1_IOCtrl_DEF *)P_TMR1_IOCtrl_ADDR; 
	P_TMR0_1_INT_DEF		*P_TMR1_INT    = (P_TMR0_1_INT_DEF *)P_TMR1_INT_ADDR;
	P_TMR0_1_Status_DEF		*P_TMR1_Status = (P_TMR0_1_Status_DEF *)P_TMR1_Status_ADDR;				

	/* C3. Timer2 register */
	P_TMR0_1_2_Ctrl_DEF		*P_TMR2_Ctrl = (P_TMR0_1_2_Ctrl_DEF *)P_TMR2_Ctrl_ADDR;;
	GEN_REG_DEF				*P_TMR2_TCNT = (GEN_REG_DEF *)P_TMR2_TCNT_ADDR;
	GEN_REG_DEF				*P_TMR2_TGRA = (GEN_REG_DEF *)P_TMR2_TGRA_ADDR;
	GEN_REG_DEF				*P_TMR2_TGRB = (GEN_REG_DEF *)P_TMR2_TGRB_ADDR;
	GEN_REG_DEF				*P_TMR2_TPR  = (GEN_REG_DEF *)P_TMR2_TPR_ADDR;
	GEN_REG_DEF				*P_TMR2_TBRA = (GEN_REG_DEF *)P_TMR2_TBRA_ADDR;
	GEN_REG_DEF				*P_TMR2_TBRB = (GEN_REG_DEF *)P_TMR2_TBRB_ADDR;
	P_TMR2_IOCtrl_DEF		*P_TMR2_IOCtrl = (P_TMR2_IOCtrl_DEF *)P_TMR2_IOCtrl_ADDR;
	P_TMR2_INT_DEF			*P_TMR2_INT    = (P_TMR2_INT_DEF *)P_TMR2_INT_ADDR;
	P_TMR2_Status_DEF		*P_TMR2_Status = (P_TMR2_Status_DEF *)P_TMR2_Status_ADDR;				

	/* C4. Timer3 register */
	P_TMR3_4_Ctrl_DEF		*P_TMR3_Ctrl = (P_TMR3_4_Ctrl_DEF *)P_TMR3_Ctrl_ADDR;
	GEN_REG_DEF				*P_TMR3_TCNT = (GEN_REG_DEF *)P_TMR3_TCNT_ADDR;
	GEN_REG_DEF				*P_TMR3_TGRA = (GEN_REG_DEF *)P_TMR3_TGRA_ADDR;
	GEN_REG_DEF				*P_TMR3_TGRB = (GEN_REG_DEF *)P_TMR3_TGRB_ADDR;
	GEN_REG_DEF				*P_TMR3_TGRC = (GEN_REG_DEF *)P_TMR3_TGRC_ADDR;
	GEN_REG_DEF				*P_TMR3_TGRD = (GEN_REG_DEF *)P_TMR3_TGRD_ADDR;
	GEN_REG_DEF				*P_TMR3_TPR  = (GEN_REG_DEF *)P_TMR3_TPR_ADDR;
	GEN_REG_DEF				*P_TMR3_TBRA = (GEN_REG_DEF *)P_TMR3_TBRA_ADDR;
	GEN_REG_DEF				*P_TMR3_TBRB = (GEN_REG_DEF *)P_TMR3_TBRB_ADDR;
	GEN_REG_DEF				*P_TMR3_TBRC = (GEN_REG_DEF *)P_TMR3_TBRC_ADDR;
	
	P_TMR3_4_IOCtrl_DEF		*P_TMR3_IOCtrl = (P_TMR3_4_IOCtrl_DEF *)P_TMR3_IOCtrl_ADDR;
	P_TMR3_4_INT_DEF		*P_TMR3_INT    = (P_TMR3_4_INT_DEF *)P_TMR3_INT_ADDR;
	P_TMR3_4_Status_DEF		*P_TMR3_Status = (P_TMR3_4_Status_DEF *)P_TMR3_Status_ADDR;				
	P_TMR3_4_OutputCtrl_DEF	*P_TMR3_OutputCtrl = (P_TMR3_4_OutputCtrl_DEF *)P_TMR3_OutputCtrl_ADDR;
	P_TMR3_4_DeadTime_DEF	*P_TMR3_DeadTime   = (P_TMR3_4_DeadTime_DEF *)P_TMR3_DeadTime_ADDR; 
	P_Fault1_2_Ctrl_DEF		*P_Fault1_Ctrl     = (P_Fault1_2_Ctrl_DEF *)P_Fault1_Ctrl_ADDR;	
	P_OL1_2_Ctrl_DEF		*P_OL1_Ctrl		   = (P_OL1_2_Ctrl_DEF *)P_OL1_Ctrl_ADDR;

	/* C5. Timer4 register */
	P_TMR3_4_Ctrl_DEF		*P_TMR4_Ctrl = (P_TMR3_4_Ctrl_DEF *)P_TMR4_Ctrl_ADDR;
	GEN_REG_DEF				*P_TMR4_TCNT = (GEN_REG_DEF *)P_TMR4_TCNT_ADDR;
	GEN_REG_DEF				*P_TMR4_TGRA = (GEN_REG_DEF *)P_TMR4_TGRA_ADDR;
	GEN_REG_DEF				*P_TMR4_TGRB = (GEN_REG_DEF *)P_TMR4_TGRB_ADDR;
	GEN_REG_DEF				*P_TMR4_TGRC = (GEN_REG_DEF *)P_TMR4_TGRC_ADDR;
	GEN_REG_DEF				*P_TMR4_TGRD = (GEN_REG_DEF *)P_TMR4_TGRD_ADDR;
	GEN_REG_DEF				*P_TMR4_TPR  = (GEN_REG_DEF *)P_TMR4_TPR_ADDR;
	GEN_REG_DEF				*P_TMR4_TBRA = (GEN_REG_DEF *)P_TMR4_TBRA_ADDR;
	GEN_REG_DEF				*P_TMR4_TBRB = (GEN_REG_DEF *)P_TMR4_TBRB_ADDR;
	GEN_REG_DEF				*P_TMR4_TBRC = (GEN_REG_DEF *)P_TMR4_TBRC_ADDR;
	
	P_TMR3_4_IOCtrl_DEF		*P_TMR4_IOCtrl = (P_TMR3_4_IOCtrl_DEF *)P_TMR4_IOCtrl_ADDR;
	P_TMR3_4_INT_DEF		*P_TMR4_INT    = (P_TMR3_4_INT_DEF *)P_TMR4_INT_ADDR;
	P_TMR3_4_Status_DEF		*P_TMR4_Status = (P_TMR3_4_Status_DEF *)P_TMR4_Status_ADDR;				
	P_TMR3_4_OutputCtrl_DEF	*P_TMR4_OutputCtrl = (P_TMR3_4_OutputCtrl_DEF *)P_TMR4_OutputCtrl_ADDR;
	P_TMR3_4_DeadTime_DEF	*P_TMR4_DeadTime   = (P_TMR3_4_DeadTime_DEF *)P_TMR4_DeadTime_ADDR; 
	P_Fault1_2_Ctrl_DEF	    *P_Fault2_Ctrl     = (P_Fault1_2_Ctrl_DEF *)P_Fault2_Ctrl_ADDR;	
	P_OL1_2_Ctrl_DEF		*P_OL2_Ctrl		   = (P_OL1_2_Ctrl_DEF *)P_OL2_Ctrl_ADDR;

	/* C6. Timer register */
	P_TMR_LDOK_DEF			*P_TMR_LDOK	  = (P_TMR_LDOK_DEF *)P_TMR_LDOK_ADDR;
	P_TMR_Start_DEF			*P_TMR_Start  = (P_TMR_Start_DEF *)P_TMR_Start_ADDR;
	P_TMR_Output_DEF		*P_TMR_Output = (P_TMR_Output_DEF *)P_TMR_Output_ADDR;
	P_TPWM_Write_DEF		*P_TPWM_Write = (P_TPWM_Write_DEF *)P_TPWM_Write_ADDR;
	
	P_POS0_1_DectCtrl_DEF	*P_POS0_DectCtrl = (P_POS0_1_DectCtrl_DEF *)P_POS0_DectCtrl_ADDR;
	P_POS0_1_DectCtrl_DEF	*P_POS1_DectCtrl = (P_POS0_1_DectCtrl_DEF *)P_POS1_DectCtrl_ADDR;

	P_POS0_DectData_DEF		*P_POS0_DectData = (P_POS0_DectData_DEF *)P_POS0_DectData_ADDR;
	P_POS1_DectData_DEF		*P_POS1_DectData = (P_POS1_DectData_DEF *)P_POS1_DectData_ADDR;
	
	P_Fault1_2_Release_DEF	*P_Fault1_Release = (P_Fault1_2_Release_DEF *)P_Fault1_Release_ADDR;		
	P_Fault1_2_Release_DEF	*P_Fault2_Release = (P_Fault1_2_Release_DEF *)P_Fault2_Release_ADDR;		
	
	/* D. ADC register */
	P_ADC_Setup_DEF 		*P_ADC_Setup 	 = (P_ADC_Setup_DEF *)P_ADC_Setup_ADDR;
	P_ADC_Ctrl_DEF          *P_ADC_Ctrl      = (P_ADC_Ctrl_DEF *)P_ADC_Ctrl_ADDR;      
	P_ADC_Data_DEF          *P_ADC_Data      = (P_ADC_Data_DEF *)P_ADC_Data_ADDR;        
	P_ADC_Channel_DEF       *P_ADC_Channel   = (P_ADC_Channel_DEF *)P_ADC_Channel_ADDR;
                                    
	/* E. SPI register */                       
	P_SPI_Ctrl_DEF        	*P_SPI_Ctrl   	 = (P_SPI_Ctrl_DEF *)P_SPI_Ctrl_ADDR;
	P_SPI_TxStatus_DEF      *P_SPI_TxStatus   = (P_SPI_TxStatus_DEF *)P_SPI_TxStatus_ADDR;
	P_SPI_TxBuf_DEF         *P_SPI_TxBuf      = (P_SPI_TxBuf_DEF *)P_SPI_TxBuf_ADDR; 
	P_SPI_RxStatus_DEF      *P_SPI_RxStatus   = (P_SPI_RxStatus_DEF *)P_SPI_RxStatus_ADDR;
	P_SPI_RxBuf_DEF         *P_SPI_RxBuf      = (P_SPI_RxBuf_DEF *)P_SPI_RxBuf_ADDR;

	/* F. Flash organization and control register */
	P_Flash_RW_DEF			*P_Flash_RW       = (P_Flash_RW_DEF *)P_Flash_RW_ADDR;
	P_Flash_Ctrl_DEF        *P_Flash_Ctrl     = (P_Flash_Ctrl_DEF *)P_Flash_Ctrl_ADDR;

	/* G. UART control register */
	P_UART_Data_DEF 		*P_UART_Data      = (P_UART_Data_DEF *)P_UART_Data_ADDR;		
	P_UART_RXStatus_DEF     *P_UART_RXStatus  = (P_UART_RXStatus_DEF *)P_UART_RXStatus_ADDR;    
	P_UART_Ctrl_DEF         *P_UART_Ctrl      = (P_UART_Ctrl_DEF *)P_UART_Ctrl_ADDR;       
	P_UART_BaudRate_DEF     *P_UART_BaudRate  = (P_UART_BaudRate_DEF *)P_UART_BaudRate_ADDR;     
	P_UART_Status_DEF       *P_UART_Status    = (P_UART_Status_DEF *)P_UART_Status_ADDR;     
	
	/* H. Compare Match Timer register */
	P_CMT_Start_DEF			*P_CMT_Start  = (P_CMT_Start_DEF *)P_CMT_Start_ADDR;
	P_CMT_Ctrl_DEF			*P_CMT_Ctrl	  = (P_CMT_Ctrl_DEF *)P_CMT_Ctrl_ADDR;
	GEN_REG_DEF				*P_CMT0_TCNT  = (GEN_REG_DEF *)P_CMT0_TCNT_ADDR;
	GEN_REG_DEF				*P_CMT1_TCNT  = (GEN_REG_DEF *)P_CMT1_TCNT_ADDR;
	GEN_REG_DEF				*P_CMT0_TPR   = (GEN_REG_DEF *)P_CMT0_TPR_ADDR;
	GEN_REG_DEF				*P_CMT1_TPR   = (GEN_REG_DEF *)P_CMT1_TPR_ADDR;
	
	/* I. Time Base register */
	GEN_REG_DEF				*P_TMB_Reset = (GEN_REG_DEF *)P_TMB_Reset_ADDR;
	P_BZO_Ctrl_DEF			*P_BZO_Ctrl  = (P_BZO_Ctrl_DEF *)P_BZO_Ctrl_ADDR;

#endif /* #ifdef SPMC751_REG_DEBUG */