?? spmc75_regs.inc
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// ========================================================================= //
// File Name : Spmc75_regs.inc //
// Description : SPMC75 series register definition //
// Processor : SPMC751FM0A //
// Author : laninlin //
// Date : May 3 2004 //
// Tools : u'nSP IDE tools v1.14.1 //
// Version : 1.00 //
// Security : Confidential Proprietary //
// E-Mail : laninlin@sunplus.com.tw //
// Revision : v1.00, Rease Version 2004/05/03 //
// ========================================================================= //
//***************************************************************************//
// A. CPU control register //
//****************************************************************************//
//****************************************************************************//
.DEFINE P_System_Option_ADDR 0x8000
.DEFINE P_Wait_Enter_ADDR 0x700C
.DEFINE P_Stdby_Enter_ADDR 0x700E
.DEFINE P_Reset_Status_ADDR 0x7006
.DEFINE P_Clk_Ctrl_ADDR 0x7007
.DEFINE P_WatchDog_Ctrl_ADDR 0x700A
.DEFINE P_WatchDog_Clr_ADDR 0x700B
.DEFINE P_Wakeup_Ctrl_ADDR 0x700F
.DEFINE P_INT_Status_ADDR 0x70A0
.DEFINE P_INT_Priority_ADDR 0x70A4
.DEFINE P_MisINT_Ctrl_ADDR 0x70A8
//***************************************************************************//
//***************************************************************************//
// B. I/O Port register //
//***************************************************************************//
//***************************************************************************//
.DEFINE P_IOA_Data_ADDR 0x7060
.DEFINE P_IOA_Buffer_ADDR 0x7061
.DEFINE P_IOA_Dir_ADDR 0x7062
.DEFINE P_IOA_Attrib_ADDR 0x7063
.DEFINE P_IOA_Latch_ADDR 0x7064
.DEFINE P_IOA_SPE_ADDR 0x7080
.DEFINE P_IOA_KCER_ADDR 0x7084
.DEFINE P_IOB_Data_ADDR 0x7068
.DEFINE P_IOB_Buffer_ADDR 0x7069
.DEFINE P_IOB_Dir_ADDR 0x706A
.DEFINE P_IOB_Attrib_ADDR 0x706B
.DEFINE P_IOB_Latch_ADDR 0x706C
.DEFINE P_IOB_SPE_ADDR 0x7081
.DEFINE P_IOC_Data_ADDR 0x7070
.DEFINE P_IOC_Buffer_ADDR 0x7071
.DEFINE P_IOC_Dir_ADDR 0x7072
.DEFINE P_IOC_Attrib_ADDR 0x7073
.DEFINE P_IOC_Latch_ADDR 0x7074
.DEFINE P_IOC_SPE_ADDR 0x7082
.DEFINE P_IOD_Data_ADDR 0x7078
.DEFINE P_IOD_Buffer_ADDR 0x7079
.DEFINE P_IOD_Dir_ADDR 0x707A
.DEFINE P_IOD_Attrib_ADDR 0x707B
.DEFINE P_IOD_Latch_ADDR 0x707C
//***************************************************************************//
//***************************************************************************//
// C. Timer 0,Timer 1,Timer 2,Timer 3,Timer 4 //
//***************************************************************************//
//***************************************************************************//
.DEFINE P_TMR0_Ctrl_ADDR 0x7400
.DEFINE P_TMR1_Ctrl_ADDR 0x7401
.DEFINE P_TMR2_Ctrl_ADDR 0x7402
.DEFINE P_TMR3_Ctrl_ADDR 0x7403
.DEFINE P_TMR4_Ctrl_ADDR 0x7404
.DEFINE P_TMR_LDOK_ADDR 0x740A
.DEFINE P_TMR0_TCNT_ADDR 0x7430
.DEFINE P_TMR1_TCNT_ADDR 0x7431
.DEFINE P_TMR2_TCNT_ADDR 0x7432
.DEFINE P_TMR3_TCNT_ADDR 0x7433
.DEFINE P_TMR4_TCNT_ADDR 0x7434
.DEFINE P_TMR0_TGRA_ADDR 0x7440
.DEFINE P_TMR0_TGRB_ADDR 0x7441
.DEFINE P_TMR0_TGRC_ADDR 0x7442
.DEFINE P_TMR1_TGRA_ADDR 0x7443
.DEFINE P_TMR1_TGRB_ADDR 0x7444
.DEFINE P_TMR1_TGRC_ADDR 0x7445
.DEFINE P_TMR2_TGRA_ADDR 0x7446
.DEFINE P_TMR2_TGRB_ADDR 0x7447
.DEFINE P_TMR3_TGRA_ADDR 0x7448
.DEFINE P_TMR3_TGRB_ADDR 0x7449
.DEFINE P_TMR3_TGRC_ADDR 0x744A
.DEFINE P_TMR3_TGRD_ADDR 0x744B
.DEFINE P_TMR4_TGRA_ADDR 0x744C
.DEFINE P_TMR4_TGRB_ADDR 0x744D
.DEFINE P_TMR4_TGRC_ADDR 0x744E
.DEFINE P_TMR4_TGRD_ADDR 0x744F
.DEFINE P_TMR0_TPR_ADDR 0x7435
.DEFINE P_TMR1_TPR_ADDR 0x7436
.DEFINE P_TMR2_TPR_ADDR 0x7437
.DEFINE P_TMR3_TPR_ADDR 0x7438
.DEFINE P_TMR4_TPR_ADDR 0x7439
.DEFINE P_TMR0_TBRA_ADDR 0x7450
.DEFINE P_TMR0_TBRB_ADDR 0x7451
.DEFINE P_TMR0_TBRC_ADDR 0x7452
.DEFINE P_TMR1_TBRA_ADDR 0x7453
.DEFINE P_TMR1_TBRB_ADDR 0x7454
.DEFINE P_TMR1_TBRC_ADDR 0x7455
.DEFINE P_TMR2_TBRA_ADDR 0x7456
.DEFINE P_TMR2_TBRB_ADDR 0x7457
.DEFINE P_TMR3_TBRA_ADDR 0x7458
.DEFINE P_TMR3_TBRB_ADDR 0x7459
.DEFINE P_TMR3_TBRC_ADDR 0x745A
.DEFINE P_TMR4_TBRA_ADDR 0x745C
.DEFINE P_TMR4_TBRB_ADDR 0x745D
.DEFINE P_TMR4_TBRC_ADDR 0x745E
.DEFINE P_TMR0_IOCtrl_ADDR 0x7410
.DEFINE P_TMR1_IOCtrl_ADDR 0x7411
.DEFINE P_TMR2_IOCtrl_ADDR 0x7412
.DEFINE P_TMR3_IOCtrl_ADDR 0x7413
.DEFINE P_TMR4_IOCtrl_ADDR 0x7414
.DEFINE P_TMR0_INT_ADDR 0x7420
.DEFINE P_TMR1_INT_ADDR 0x7421
.DEFINE P_TMR2_INT_ADDR 0x7422
.DEFINE P_TMR3_INT_ADDR 0x7423
.DEFINE P_TMR4_INT_ADDR 0x7424
.DEFINE P_TMR0_Status_ADDR 0x7425
.DEFINE P_TMR1_Status_ADDR 0x7426
.DEFINE P_TMR2_Status_ADDR 0x7427
.DEFINE P_TMR3_Status_ADDR 0x7428
.DEFINE P_TMR4_Status_ADDR 0x7429
.DEFINE P_TMR_Start_ADDR 0x7405
.DEFINE P_TMR_Output_ADDR 0x7406
.DEFINE P_TMR3_OutputCtrl_ADDR 0x7407
.DEFINE P_TMR4_OutputCtrl_ADDR 0x7408
.DEFINE P_POS0_DectCtrl_ADDR 0x7462
.DEFINE P_POS1_DectCtrl_ADDR 0x7463
.DEFINE P_POS0_DectData_ADDR 0x7464
.DEFINE P_POS1_DectData_ADDR 0x7465
.DEFINE P_TMR3_DeadTime_ADDR 0x7460
.DEFINE P_TMR4_DeadTime_ADDR 0x7461
.DEFINE P_TPWM_Write_ADDR 0x7409
.DEFINE P_TMR3_FaultCtrl_ADDR 0x7466
.DEFINE P_TMR4_FaultCtrl_ADDR 0x7467
.DEFINE P_TMR3_OLProtect_ADDR 0x7468
.DEFINE P_TMR4_OLProtect_ADDR 0x7469
.DEFINE P_Fault1_Release_ADDR 0x746A
.DEFINE P_Fault2_Release_ADDR 0x746B
//***************************************************************************//
//***************************************************************************//
// D. 10-bit ADC converter register //
//***************************************************************************//
//***************************************************************************//
.DEFINE P_ADC_Setup_ADDR 0x7160
.DEFINE P_ADC_Ctrl_ADDR 0x7161
.DEFINE P_ADC_Data_ADDR 0x7162
.DEFINE P_ADC_Channel_ADDR 0x7166
//***************************************************************************//
//***************************************************************************//
// E. Standard Peripheral Interface SPI register //
//***************************************************************************//
//***************************************************************************//
.DEFINE P_SPI_Ctrl_ADDR 0x7140
.DEFINE P_SPI_TxStatus_ADDR 0x7141
.DEFINE P_SPI_TxBuf_ADDR 0x7142
.DEFINE P_SPI_RxStatus_ADDR 0x7143
.DEFINE P_SPI_RxBuf_ADDR 0x7144
//***************************************************************************//
//***************************************************************************//
// F. Flash organization and control register //
//***************************************************************************//
//***************************************************************************//
.DEFINE P_Flash_RW_ADDR 0x7554
.DEFINE P_Flash_Ctrl_ADDR 0x7555
//***************************************************************************//
//***************************************************************************//
// G. UART Control Register //
//***************************************************************************//
//***************************************************************************//
.DEFINE P_UART_Data_ADDR 0x7100
.DEFINE P_UART_RXStatus_ADDR 0x7101
.DEFINE P_UART_Ctrl_ADDR 0x7102
.DEFINE P_UART_BaudRate_ADDR 0x7103
.DEFINE P_UART_Status_ADDR 0x7104
//***************************************************************************//
//***************************************************************************//
// H. Compare Match Timer Register //
//***************************************************************************//
//***************************************************************************//
.DEFINE P_CMT_Start_ADDR 0x7500
.DEFINE P_CMT_Ctrl_ADDR 0x7501
.DEFINE P_CMT0_TCNT_ADDR 0x7508
.DEFINE P_CMT1_TCNT_ADDR 0x7509
.DEFINE P_CMT0_TPR_ADDR 0x7510
.DEFINE P_CMT1_TPR_ADDR 0x7511
//***************************************************************************//
//***************************************************************************//
// I. Time Base Register //
//***************************************************************************//
//***************************************************************************//
.DEFINE P_TMB_Reset_ADDR 0x70B8
.DEFINE P_BZO_Ctrl_ADDR 0x70B9
//========================================================================================
//Constant Definition
//========================================================================================
// Timer Base Setup --- [P_TimeBase_Setup]
.define C_TMBDIS 0x0010 //Disable TimeBase
.define C_TMBENB 0x0000 //Enable TimeBase
.define C_TMB2FS_128HZ 0x0000 //Set TimeBase2 as 128 HZ
.define C_TMB2FS_256HZ 0x0004 //Set TimeBase2 as 256 HZ
.define C_TMB2FS_512HZ 0x0008 //Set TimeBase2 as 512 HZ
.define C_TMB2FS_1024HZ 0x000C //Set TimeBase2 as 1024 HZ
.define C_TMB1FS_8HZ 0x0000 //Set TimeBase1 as 8 HZ
.define C_TMB1FS_16HZ 0x0001 //Set TimeBase1 as 16 HZ
.define C_TMB1FS_32HZ 0x0002 //Set TimeBase1 as 32 HZ
.define C_TMB1FS_64HZ 0x0003 //Set TimeBase1 as 64 HZ
//=================================//
// flash control register //
//=================================//
// P_Wait_Enter register //
// word set //
.DEFINE CW_WaitCMD 0x5005
.DEFINE CW_WaitClr 0x0001
// P_Stdby_Enter register //
// word set //
.DEFINE CW_StdbyCMD 0xA00A
.DEFINE CW_StdbyClr 0x0001
// P_System_Option register //
// word set //
.DEFINE CW_SYS_CLK_R 0x0000
.DEFINE CW_SYS_CLK_OSC 0x0001
.DEFINE CW_SYS_WDG_Disable (0x0000 << 1)
.DEFINE CW_SYS_WDG_Enable (0x0001 << 1)
.DEFINE CW_SYS_LVR_Disable (0x0000 << 2)
.DEFINE CW_SYS_LVR_Enable (0x0001 << 2)
.DEFINE CW_SYS_LVD_Disable (0x0000 << 3)
.DEFINE CW_SYS_LVD_Enable (0x0001 << 3)
.DEFINE CW_SYS_Security_Protect (0x0000 << 4)
.DEFINE CW_SYS_Security_NoProtect (0x0001 << 4)
.DEFINE CW_SYS_Verification (0x02AA << 5)
// P_Reset_Status register //
// word set //
.DEFINE CW_CLEAR_EXTRF 0x0001
.DEFINE CW_CLEAR_PORF (0x0001 << 1)
.DEFINE CW_CLEAR_WDRF (0x0001 << 2)
.DEFINE CW_CLEAR_LPLVRF (0x0001 << 3)
.DEFINE CW_CLEAR_SPLVRF (0x0001 << 4)
.DEFINE CW_CLEAR_IARF (0x0001 << 5)
.DEFINE CW_CLEAR_IIRF (0x0001 << 6)
.DEFINE CW_CLEAR_FCHK (0x0055 << 9)
// P_Clk_Ctrl register //
// word set //
.DEFINE CW_CLK_OSCIE (0x0001 << 14)
.DEFINE CW_CLK_OSCSF (0x0001 << 15)
// P_WatchDog_Ctrl register //
// word set //
.DEFINE CW_WDPS_FCKdiv65536 0x0000
.DEFINE CW_WDPS_FCKdiv32768 0x0001
.DEFINE CW_WDPS_FCKdiv16384 0x0002
.DEFINE CW_WDPS_FCKdiv8192 0x0003
.DEFINE CW_WDPS_FCKdiv4096 0x0004
.DEFINE CW_WDPS_FCKdiv2048 0x0005
.DEFINE CW_WDPS_FCKdiv1024 0x0006
.DEFINE CW_WDPS_FCKdiv512 0x0007
.DEFINE CW_WDCHK_Setting (0x0015 << 3)
.DEFINE CW_WDRS_SYS_Reset (0x0000 << 14)
.DEFINE CW_WDRS_CPU_Reset (0x0001 << 14)
.DEFINE CW_WDEN (0x0001 << 15)
.DEFINE CW_WatchDog_Clear 0xA005
// P_Wakeup_Ctrl register //
// word set //
.DEFINE CW_CMTWE_Enable (0x0001<<4)
.DEFINE CW_TPM0WE_Enable (0x0001<<5)
.DEFINE CW_TPM1WE_Enable (0x0001<<6)
.DEFINE CW_TPM2WE_Enable (0x0001<<7)
.DEFINE CW_EXT0WE_Enable (0x0001<<11)
.DEFINE CW_EXT1WE_Enable (0x0001<<12)
.DEFINE CW_SPIWE_Enable (0x0001<<13)
.DEFINE CW_UARTWE_Enable (0x0001<<14)
.DEFINE CW_KEYWE_Enable (0x0001<<15)
// P_Flash_RW register //
// word set //
.DEFINE CW_BK15WDIS 0x4000 //BANK 15 Write Disable
.DEFINE CW_BK14WDIS 0x4000 //BANK 14 Write Disable
.DEFINE CW_BK13WDIS 0x2000 //BANK 13 Write Disable
.DEFINE CW_BK12WDIS 0x1000 //BANK 12 Write Disable
.DEFINE CW_BK11WDIS 0x0800 //BANK 11 Write Disable
.DEFINE CW_BK10WDIS 0x0400 //BANK 10 Write Disable
.DEFINE CW_BK9WDIS 0x0200 //BANK 9 Write Disable
.DEFINE CW_BK8WDIS 0x0100 //BANK 8 Write Disable
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