?? spmc75_regs.inc
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.DEFINE CW_BK7WDIS 0x0080 //BANK 7 Write Disable
.DEFINE CW_BK6WDIS 0x0040 //BANK 6 Write Disable
.DEFINE CW_BK5WDIS 0x0020 //BANK 5 Write Disable
.DEFINE CW_BK4WDIS 0x0010 //BANK 4 Write Disable
.DEFINE CW_BK3WDIS 0x0008 //BANK 3 Write Disable
.DEFINE CW_BK2WDIS 0x0004 //BANK 2 Write Disable
.DEFINE CW_BK1WDIS 0x0002 //BANK 1 Write Disable
.DEFINE CW_BK0WDIS 0x0001 //BANK 0 Write Disable
// P_Flash_Ctrl register //
// word set //
.DEFINE CW_FlashRW_CMD 0x5A5A //Flash RW Command
.DEFINE CW_FlashCMD 0xAAAA //Flash Command FLash Block
.DEFINE CW_PageErase 0x5511 //Flash Page Erase Command
.DEFINE CW_Program 0x5533 //Flash Program Command
.DEFINE CW_Sequential 0x5544 //Flash Sequential Program Command
.DEFINE CW_SequentialEnd 0xFFFF //Flash Sequential Program End Command
// P_IOA_SPE register //
// word set //
.DEFINE CW_IOA_TMR2_TGRA_SFR_EN 0x0200 //TGRA of Timer2 special function enable
.DEFINE CW_IOA_TMR2_TGRB_SFR_EN 0x0400 //TGRB of Timer2 special function enable
.DEFINE CW_IOA_TCLKA_SFR_EN 0x0800 //External clock A input enable
.DEFINE CW_IOA_TCLKB_SFR_EN 0x1000 //External clock B input enable
.DEFINE CW_IOA_TCLKC_SFR_EN 0x2000 //External clock C input enable
.DEFINE CW_IOA_TCLKD_SFREN 0x4000 //External clock D input enable
// P_IOA_KCER register //
// word set //
.DEFINE CW_IOA_KC8_EN 0x0100 //IOA8 key change enable
.DEFINE CW_IOA_KC9_EN 0x0200 //IOA9 key change enable
.DEFINE CW_IOA_KC10_EN 0x0400 //IOA10 key change enable
.DEFINE CW_IOA_KC11_EN 0x0800 //IOA11 key change enable
.DEFINE CW_IOA_KC12_EN 0x1000 //IOA12 key change enable
.DEFINE CW_IOA_KC13_EN 0x2000 //IOA13 key change enable
.DEFINE CW_IOA_KC14_EN 0x4000 //IOA14 key change enable
.DEFINE CW_IOA_KC15_EN 0x8000 //IOA15 key change enable
// P_IOB_SPE register //
// word set //
.DEFINE CW_IOB_W1N_SFR_EN 0x0001 //IOB0 serves as W1N
.DEFINE CW_IOB_V1N_SFR_EN 0x0002 //IOB1 serves as V1N
.DEFINE CW_IOB_U1N_SFR_EN 0x0004 //IOB2 serves as U1N
.DEFINE CW_IOB_W1_SFR_EN 0x0008 //IOB3 serves as W1
.DEFINE CW_IOB_V1_SFR_EN 0x0010 //IOB4 serves as V1
.DEFINE CW_IOB_U1_SFR_EN 0x0020 //IOB5 serves as U1
.DEFINE CW_IOB_FTIN1_SFR_EN 0x0040 //IOB6 serves as FTIN1
.DEFINE CW_IOB_OL1_SFR_EN 0x0080 //IOB7 serves as OL1
.DEFINE CW_IOB_TMR0_TGRC_SFR_EN 0x0100 //TGRC of Timer0 special function enable
.DEFINE CW_IOB_TMR0_TGRB_SFR_EN 0x0200 //TGRB of Timer0 special function enable
.DEFINE CW_IOB_TMR0_TGRA_SFR_EN 0x0400 //TGRA of Timer0 special function enable
// P_IOC_SPE register //
// word set //
.DEFINE CW_IOC_EXTINT0_SFR_EN 0x0004 //IOC2 external input interrupt 0 enable
.DEFINE CW_IOC_EXTINT1_SFR_EN 0x0008 //IOC3 external input interrupt 0 enable
.DEFINE CW_IOC_TMR1_TGRA_SFR_EN 0x0010 //TGRA of Timer1 special function enable
.DEFINE CW_IOC_TMR1_TGRB_SFR_EN 0x0020 //TGRB of Timer1 special function enable
.DEFINE CW_IOC_TMR1_TGRC_SFR_EN 0x0040 //TGRC of Timer1 special function enable
.DEFINE CW_IOC_OL2_SFR_EN 0x0100 //IOC8 serves as OL2
.DEFINE CW_IOC_FTIN2_SFR_EN 0x0200 //IOC9 serves as FTIN2
.DEFINE CW_IOC_U2_SFR_EN 0x0400 //IOC10 serves as U2
.DEFINE CW_IOC_V2_SFR_EN 0x0800 //IOC11 serves as V2
.DEFINE CW_IOC_W2_SFR_EN 0x1000 //IOC12 serves as W2
.DEFINE CW_IOC_U2N_SFR_EN 0x2000 //IOC13 serves as U2N
.DEFINE CW_IOC_V2N_SFR_EN 0x4000 //IOC14 serves as V2N
.DEFINE CW_IOC_W2N_SFR_EN 0x8000 //IOC15 serves as W2N
//=================================//
// B. Timer0/Timer1/Timer2 register//
//=================================//
// P_TMR0_Ctrl register //
// word set //
.DEFINE CW_TMR0_TMRPS_FCKdiv1 0x0000
.DEFINE CW_TMR0_TMRPS_FCKdiv4 0x0001
.DEFINE CW_TMR0_TMRPS_FCKdiv16 0x0002
.DEFINE CW_TMR0_TMRPS_FCKdiv64 0x0003
.DEFINE CW_TMR0_TMRPS_FCKdiv256 0x0004
.DEFINE CW_TMR0_TMRPS_FCKdiv1024 0x0005
.DEFINE CW_TMR0_TMRPS_TCLKA 0x0006
.DEFINE CW_TMR0_TMRPS_TCLKB 0x0007
.DEFINE CW_TMR0_CKEGS_Rising (0x0000 << 3)
.DEFINE CW_TMR0_CKEGS_Falling (0x0001 << 3)
.DEFINE CW_TMR0_CKEGS_Both (0x0002 << 3)
.DEFINE CW_TMR0_CCLS_Disabled (0x0000 << 5)
.DEFINE CW_TMR0_CCLS_TGRA (0x0001 << 5)
.DEFINE CW_TMR0_CCLS_TGRB (0x0002 << 5)
.DEFINE CW_TMR0_CCLS_TGRC (0x0003 << 5)
.DEFINE CW_TMR0_CCLS_PDR3 (0x0004 << 5)
.DEFINE CW_TMR0_CCLS_PDR6 (0x0005 << 5)
.DEFINE CW_TMR0_CCLS_PPR (0x0006 << 5)
.DEFINE CW_TMR0_CCLS_PTR (0x0007 << 5)
.DEFINE CW_TMR0_CLEGS_NotClear (0x0000 << 8)
.DEFINE CW_TMR0_CLEGS_Rising (0x0001 << 8)
.DEFINE CW_TMR0_CLEGS_Falling (0x0002 << 8)
.DEFINE CW_TMR0_CLEGS_Both (0x0003 << 8)
.DEFINE CW_TMR0_MODE_Normal (0x0000 << 10)
.DEFINE CW_TMR0_MODE_Mode1 (0x0004 << 10)
.DEFINE CW_TMR0_MODE_Mode2 (0x0005 << 10)
.DEFINE CW_TMR0_MODE_Mode3 (0x0006 << 10)
.DEFINE CW_TMR0_MODE_Mode4 (0x0007 << 10)
.DEFINE CW_TMR0_MODE_PWM_Edge (0x0008 << 10)
.DEFINE CW_TMR0_MODE_PWM_Center (0x000A << 10)
.DEFINE CW_TMR0_SPCK_FCKdiv1 (0x0000 << 14)
.DEFINE CW_TMR0_SPCK_FCKdiv2 (0x0001 << 14)
.DEFINE CW_TMR0_SPCK_FCKdiv4 (0x0002 << 14)
.DEFINE CW_TMR0_SPCK_FCKdiv8 (0x0003 << 14)
// P_TMR1_Ctrl register //
// word set //
.DEFINE CW_TMR1_TMRPS_FCKdiv1 0x0000
.DEFINE CW_TMR1_TMRPS_FCKdiv4 0x0001
.DEFINE CW_TMR1_TMRPS_FCKdiv16 0x0002
.DEFINE CW_TMR1_TMRPS_FCKdiv64 0x0003
.DEFINE CW_TMR1_TMRPS_FCKdiv256 0x0004
.DEFINE CW_TMR1_TMRPS_FCKdiv1024 0x0005
.DEFINE CW_TMR1_TMRPS_TCLKA 0x0006
.DEFINE CW_TMR1_TMRPS_TCLKB 0x0007
.DEFINE CW_TMR1_CKEGS_Rising (0x0000 << 3)
.DEFINE CW_TMR1_CKEGS_Falling (0x0001 << 3)
.DEFINE CW_TMR1_CKEGS_Both (0x0002 << 3)
.DEFINE CW_TMR1_CCLS_Disabled (0x0000 << 5)
.DEFINE CW_TMR1_CCLS_TGRA (0x0001 << 5)
.DEFINE CW_TMR1_CCLS_TGRB (0x0002 << 5)
.DEFINE CW_TMR1_CCLS_TGRC (0x0003 << 5)
.DEFINE CW_TMR1_CCLS_PDR3 (0x0004 << 5)
.DEFINE CW_TMR1_CCLS_PDR6 (0x0005 << 5)
.DEFINE CW_TMR1_CCLS_PPR (0x0006 << 5)
.DEFINE CW_TMR1_CCLS_PTR (0x0007 << 5)
.DEFINE CW_TMR1_CLEGS_NotClear (0x0000 << 8)
.DEFINE CW_TMR1_CLEGS_Rising (0x0001 << 8)
.DEFINE CW_TMR1_CLEGS_Falling (0x0002 << 8)
.DEFINE CW_TMR1_CLEGS_Both (0x0003 << 8)
.DEFINE CW_TMR1_MODE_Normal (0x0000 << 10)
.DEFINE CW_TMR1_MODE_Mode1 (0x0004 << 10)
.DEFINE CW_TMR1_MODE_Mode2 (0x0005 << 10)
.DEFINE CW_TMR1_MODE_Mode3 (0x0006 << 10)
.DEFINE CW_TMR1_MODE_Mode4 (0x0007 << 10)
.DEFINE CW_TMR1_MODE_PWM_Edge (0x0008 << 10)
.DEFINE CW_TMR1_MODE_PWM_Center (0x000A << 10)
.DEFINE CW_TMR1_SPCK_FCKdiv1 (0x0000 << 14)
.DEFINE CW_TMR1_SPCK_FCKdiv2 (0x0001 << 14)
.DEFINE CW_TMR1_SPCK_FCKdiv4 (0x0002 << 14)
.DEFINE CW_TMR1_SPCK_FCKdiv8 (0x0003 << 14)
// P_TMR2_Ctrl register //
// word set //
.DEFINE CW_TMR2_TMRPS_FCKdiv1 0x0000
.DEFINE CW_TMR2_TMRPS_FCKdiv4 0x0001
.DEFINE CW_TMR2_TMRPS_FCKdiv16 0x0002
.DEFINE CW_TMR2_TMRPS_FCKdiv64 0x0003
.DEFINE CW_TMR2_TMRPS_FCKdiv256 0x0004
.DEFINE CW_TMR2_TMRPS_FCKdiv1024 0x0005
.DEFINE CW_TMR2_TMRPS_TCLKA 0x0006
.DEFINE CW_TMR2_TMRPS_TCLKB 0x0007
.DEFINE CW_TMR2_CKEGS_Rising (0x0000 << 3)
.DEFINE CW_TMR2_CKEGS_Falling (0x0001 << 3)
.DEFINE CW_TMR2_CKEGS_Both (0x0002 << 3)
.DEFINE CW_TMR2_CCLS_Disabled (0x0000 << 5)
.DEFINE CW_TMR2_CCLS_TGRA (0x0001 << 5)
.DEFINE CW_TMR2_CCLS_TGRB (0x0002 << 5)
.DEFINE CW_TMR2_CCLS_PTR (0x0007 << 5)
.DEFINE CW_TMR2_CLEGS_NotClear (0x0000 << 8)
.DEFINE CW_TMR2_CLEGS_Rising (0x0001 << 8)
.DEFINE CW_TMR2_CLEGS_Falling (0x0002 << 8)
.DEFINE CW_TMR2_CLEGS_Both (0x0003 << 8)
.DEFINE CW_TMR2_MODE_Normal (0x0000 << 10)
.DEFINE CW_TMR2_MODE_PWM_Edge (0x0008 << 10)
.DEFINE CW_TMR2_MODE_PWM_Center (0x000A << 10)
.DEFINE CW_TMR2_SPCK_FCKdiv1 (0x0000 << 14)
.DEFINE CW_TMR2_SPCK_FCKdiv2 (0x0001 << 14)
.DEFINE CW_TMR2_SPCK_FCKdiv4 (0x0002 << 14)
.DEFINE CW_TMR2_SPCK_FCKdiv8 (0x0003 << 14)
// P_TMR3_Ctrl register //
// word set //
.DEFINE CW_TMR3_TMRPS_FCKdiv1 0x0000
.DEFINE CW_TMR3_TMRPS_FCKdiv4 0x0001
.DEFINE CW_TMR3_TMRPS_FCKdiv16 0x0002
.DEFINE CW_TMR3_TMRPS_FCKdiv64 0x0003
.DEFINE CW_TMR3_TMRPS_FCKdiv256 0x0004
.DEFINE CW_TMR3_TMRPS_FCKdiv1024 0x0005
.DEFINE CW_TMR3_TMRPS_TCLKA 0x0006
.DEFINE CW_TMR3_TMRPS_TCLKB 0x0007
.DEFINE CW_TMR3_CKEGS_Rising (0x0000 << 3)
.DEFINE CW_TMR3_CKEGS_Falling (0x0001 << 3)
.DEFINE CW_TMR3_CKEGS_Both (0x0002 << 3)
.DEFINE CW_TMR3_CCLS_Disabled (0x0000 << 5)
.DEFINE CW_TMR3_CCLS_PTR (0x0007 << 5)
//.DEFINE CW_TMR3_LDOK (0x0001 << 9)
.DEFINE CW_TMR3_MODE_Normal (0x0000 << 10)
.DEFINE CW_TMR3_MODE_PWM_Edge (0x0008 << 10)
.DEFINE CW_TMR3_MODE_PWM_Center (0x000A << 10)
.DEFINE CW_TMR3_PRDINT_Period (0x0000 << 14)
.DEFINE CW_TMR3_PRDINT_2Period (0x0001 << 14)
.DEFINE CW_TMR3_PRDINT_4Period (0x0002 << 14)
.DEFINE CW_TMR3_PRDINT_8Period (0x0003 << 14)
// P_TMR4_Ctrl register //
// word set //
.DEFINE CW_TMR4_TMRPS_FCKdiv1 0x0000
.DEFINE CW_TMR4_TMRPS_FCKdiv4 0x0001
.DEFINE CW_TMR4_TMRPS_FCKdiv16 0x0002
.DEFINE CW_TMR4_TMRPS_FCKdiv64 0x0003
.DEFINE CW_TMR4_TMRPS_FCKdiv256 0x0004
.DEFINE CW_TMR4_TMRPS_FCKdiv1024 0x0005
.DEFINE CW_TMR4_TMRPS_TCLKA 0x0006
.DEFINE CW_TMR4_TMRPS_TCLKB 0x0007
.DEFINE CW_TMR4_CKEGS_Rising (0x0000 << 3)
.DEFINE CW_TMR4_CKEGS_Falling (0x0001 << 3)
.DEFINE CW_TMR4_CKEGS_Both (0x0002 << 3)
.DEFINE CW_TMR4_CCLS_Disabled (0x0000 << 5)
.DEFINE CW_TMR4_CCLS_PTR (0x0007 << 5)
//.DEFINE CW_TMR4_LDOK (0x0001 << 9)
.DEFINE CW_TMR4_MODE_Normal (0x0000 << 10)
.DEFINE CW_TMR4_MODE_PWM_Edge (0x0008 << 10)
.DEFINE CW_TMR4_MODE_PWM_Center (0x000A << 10)
.DEFINE CW_TMR4_PRDINT_Period (0x0000 << 14)
.DEFINE CW_TMR4_PRDINT_2Period (0x0001 << 14)
.DEFINE CW_TMR4_PRDINT_4Period (0x0002 << 14)
.DEFINE CW_TMR4_PRDINT_8Period (0x0003 << 14)
// P_TMR0_IOCtrl register //
// word set //
.DEFINE CW_TMR0_IOAMOD_Output_00 0x0000
.DEFINE CW_TMR0_IOAMOD_Output_01 0x0001
.DEFINE CW_TMR0_IOAMOD_Output_10 0x0002
.DEFINE CW_TMR0_IOAMOD_Output_11 0x0003
.DEFINE CW_TMR0_IOAMOD_Output_Hold 0x0004
.DEFINE CW_TMR0_IOAMOD_Capture_Rising 0x0008
.DEFINE CW_TMR0_IOAMOD_Capture_Falling 0x0009
.DEFINE CW_TMR0_IOAMOD_Capture_Both 0x000A
.DEFINE CW_TMR0_IOAMOD_Capture_PDR 0x000C
.DEFINE CW_TMR0_IOBMOD_Output_00 (0x0000 << 4)
.DEFINE CW_TMR0_IOBMOD_Output_01 (0x0001 << 4)
.DEFINE CW_TMR0_IOBMOD_Output_10 (0x0002 << 4)
.DEFINE CW_TMR0_IOBMOD_Output_11 (0x0003 << 4)
.DEFINE CW_TMR0_IOBMOD_Output_Hold (0x0004 << 4)
.DEFINE CW_TMR0_IOBMOD_Capture_Rising (0x0008 << 4)
.DEFINE CW_TMR0_IOBMOD_Capture_Falling (0x0009 << 4)
.DEFINE CW_TMR0_IOBMOD_Capture_Both (0x000A << 4)
.DEFINE CW_TMR0_IOBMOD_Capture_PDR (0x000C << 4)
.DEFINE CW_TMR0_IOCMOD_Output_00 (0x0000 << 8)
.DEFINE CW_TMR0_IOCMOD_Output_01 (0x0001 << 8)
.DEFINE CW_TMR0_IOCMOD_Output_10 (0x0002 << 8)
.DEFINE CW_TMR0_IOCMOD_Output_11 (0x0003 << 8)
.DEFINE CW_TMR0_IOCMOD_Output_Hold (0x0004 << 8)
.DEFINE CW_TMR0_IOCMOD_Capture_Rising (0x0008 << 8)
.DEFINE CW_TMR0_IOCMOD_Capture_Falling (0x0009 << 8)
.DEFINE CW_TMR0_IOCMOD_Capture_Both (0x000A << 8)
.DEFINE CW_TMR0_IOCMOD_Capture_PDR (0x000C << 8)
// P_TMR1_IOCtrl register //
// word set //
.DEFINE CW_TMR1_IOAMOD_Output_00 0x0000
.DEFINE CW_TMR1_IOAMOD_Output_01 0x0001
.DEFINE CW_TMR1_IOAMOD_Output_10 0x0002
.DEFINE CW_TMR1_IOAMOD_Output_11 0x0003
.DEFINE CW_TMR1_IOAMOD_Output_Hold 0x0004
.DEFINE CW_TMR1_IOAMOD_Capture_Rising 0x0008
.DEFINE CW_TMR1_IOAMOD_Capture_Falling 0x0009
.DEFINE CW_TMR1_IOAMOD_Capture_Both 0x000A
.DEFINE CW_TMR1_IOAMOD_Capture_PDR 0x000C
.DEFINE CW_TMR1_IOBMOD_Output_00 (0x0000 << 4)
.DEFINE CW_TMR1_IOBMOD_Output_01 (0x0001 << 4)
.DEFINE CW_TMR1_IOBMOD_Output_10 (0x0002 << 4)
.DEFINE CW_TMR1_IOBMOD_Output_11 (0x0003 << 4)
.DEFINE CW_TMR1_IOBMOD_Output_Hold (0x0004 << 4)
.DEFINE CW_TMR1_IOBMOD_Capture_Rising (0x0008 << 4)
.DEFINE CW_TMR1_IOBMOD_Capture_Falling (0x0009 << 4)
.DEFINE CW_TMR1_IOBMOD_Capture_Both (0x000A << 4)
.DEFINE CW_TMR1_IOBMOD_Capture_PDR (0x000C << 4)
.DEFINE CW_TMR1_IOCMOD_Output_00 (0x0000 << 8)
.DEFINE CW_TMR1_IOCMOD_Output_01 (0x0001 << 8)
.DEFINE CW_TMR1_IOCMOD_Output_10 (0x0002 << 8)
.DEFINE CW_TMR1_IOCMOD_Output_11 (0x0003 << 8)
.DEFINE CW_TMR1_IOCMOD_Output_Hold (0x0004 << 8)
.DEFINE CW_TMR1_IOCMOD_Capture_Rising (0x0008 << 8)
.DEFINE CW_TMR1_IOCMOD_Capture_Falling (0x0009 << 8)
.DEFINE CW_TMR1_IOCMOD_Capture_Both (0x000A << 8)
.DEFINE CW_TMR1_IOCMOD_Capture_PDR (0x000C << 8)
// P_TMR2_IOCtrl register //
// word set //
.DEFINE CW_TMR2_IOAMOD_Output_00 0x0000
.DEFINE CW_TMR2_IOAMOD_Output_01 0x0001
.DEFINE CW_TMR2_IOAMOD_Output_10 0x0002
.DEFINE CW_TMR2_IOAMOD_Output_11 0x0003
.DEFINE CW_TMR2_IOAMOD_Output_Hold 0x0004
.DEFINE CW_TMR2_IOAMOD_Capture_Rising 0x0008
.DEFINE CW_TMR2_IOAMOD_Capture_Falling 0x0009
.DEFINE CW_TMR2_IOAMOD_Capture_Both 0x000A
.DEFINE CW_TMR2_IOBMOD_Output_00 (0x0000 << 4)
.DEFINE CW_TMR2_IOBMOD_Output_01 (0x0001 << 4)
.DEFINE CW_TMR2_IOBMOD_Output_10 (0x0002 << 4)
.DEFINE CW_TMR2_IOBMOD_Output_11 (0x0003 << 4)
.DEFINE CW_TMR2_IOBMOD_Output_Hold (0x0004 << 4)
.DEFINE CW_TMR2_IOBMOD_Capture_Rising (0x0008 << 4)
.DEFINE CW_TMR2_IOBMOD_Capture_Falling (0x0009 << 4)
.DEFINE CW_TMR2_IOBMOD_Capture_Both (0x000A << 4)
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