?? mmucache.h
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/*****************************************
NAME: MMU.H
DESC: MMU Header
HISTORY:
2003.04.04 : ver 0.0
******************************************/
#ifndef __MMUCACHE_H__
#define __MMUCACHE_H__
#ifdef __cplusplus
extern "C" {
#endif
int SET_IF(void);
void WR_IF(int cpsrValue);
void CLR_IF(void);
void ChangeClockDivider(unsigned int hdivn,unsigned int pdivn);
// hdivn,pdivn FCLK:HCLK:PCLK
// 0,0 1:1:1
// 0,1 1:1:2
// 1,0 1:2:2
// 1,1 1:2:4
void EnterStopMode(void);
void MMU_EnableMIDCache(void);
/*
;void MMU_EnableMIDCache(void)
EXPORT MMU_EnableMIDCache
MMU_EnableMIDCache
mrc p15,0,r0,c1,c0,0
orr r0,r0,#R1_M
orr r0,r0,#R1_I
orr r0,r0,#R1_C
mcr p15,0,r0,c1,c0,0
MOV_PC_LR
*/
void MMU_EnableICache(void);
/*
;void MMU_EnableICache(void)
EXPORT MMU_EnableICache
MMU_EnableICache
mrc p15,0,r0,c1,c0,0
orr r0,r0,#R1_I
mcr p15,0,r0,c1,c0,0
MOV_PC_LR
*/
void MMU_DisableICache(void);
/*
;void MMU_DisableICache(void)
EXPORT MMU_DisableICache
MMU_DisableICache
mrc p15,0,r0,c1,c0,0
bic r0,r0,#R1_I
mcr p15,0,r0,c1,c0,0
MOV_PC_LR
*/
void MMU_EnableDCache(void);
/*
;void MMU_EnableDCache(void)
EXPORT MMU_EnableDCache
MMU_EnableDCache
mrc p15,0,r0,c1,c0,0
orr r0,r0,#R1_C
mcr p15,0,r0,c1,c0,0
MOV_PC_LR
*/
void MMU_DisableDCache(void);
/*
;void MMU_DisableDCache(void)
EXPORT MMU_DisableDCache
MMU_DisableDCache
mrc p15,0,r0,c1,c0,0
bic r0,r0,#R1_C
mcr p15,0,r0,c1,c0,0
MOV_PC_LR
*/
void MMU_EnableAlignFault(void);
/*
;void MMU_EnableAlignFault(void)
EXPORT MMU_EnableAlignFault
MMU_EnableAlignFault
mrc p15,0,r0,c1,c0,0
orr r0,r0,#R1_A
mcr p15,0,r0,c1,c0,0
MOV_PC_LR
*/
void MMU_DisableAlignFault(void);
/*
;void MMU_DisableAlignFault(void)
EXPORT MMU_DisableAlignFault
MMU_DisableAlignFault
mrc p15,0,r0,c1,c0,0
bic r0,r0,#R1_A
mcr p15,0,r0,c1,c0,0
MOV_PC_LR
*/
void MMU_EnableMMU(void);
/*
;void MMU_EnableMMU(void)
EXPORT MMU_EnableMMU
MMU_EnableMMU
mrc p15,0,r0,c1,c0,0
orr r0,r0,#R1_M
mcr p15,0,r0,c1,c0,0
MOV_PC_LR
*/
void MMU_DisableMMU(void);
/*
;void MMU_DisableMMU(void)
EXPORT MMU_DisableMMU
MMU_DisableMMU
mrc p15,0,r0,c1,c0,0
bic r0,r0,#R1_M
mcr p15,0,r0,c1,c0,0
MOV_PC_LR
*/
void MMU_SetTTBase(unsigned int base);
/*
;void MMU_SetTTBase(int base)
EXPORT MMU_SetTTBase
MMU_SetTTBase
;r0=TTBase
mcr p15,0,r0,c2,c0,0
MOV_PC_LR
*/
void MMU_SetDomain(unsigned int domain);
/*
;void MMU_SetDomain(int domain)
EXPORT MMU_SetDomain
MMU_SetDomain
;r0=domain
mcr p15,0,r0,c3,c0,0
MOV_PC_LR
*/
//int MMU_ReadDomain(void);
/*
;int MMU_ReadDomain(void)
EXPORT MMU_ReadDomain
MMU_ReadDomain
;r0=domain
mrc p15,0,r0,c3,c0,0
MOV_PC_LR
*/
int MMU_ReadDFSR(void);
/*
EXPORT MMU_ReadDFSR
MMU_ReadDFSR
;r0=DFSR
mrc p15,0,r0,c5,c0,0
MOV_PC_LR
*/
int MMU_ReadIFSR(void);
/*
EXPORT MMU_ReadIFSR
MMU_ReadIFSR
;r0=IFSR
mrc p15,0,r0,c5,c0,1
MOV_PC_LR
*/
int MMU_ReadFAR(void);
/*
EXPORT MMU_ReadFAR
MMU_ReadFAR
;r0=FAR
mrc p15,0,r0,c6,c0,0
MOV_PC_LR
*/
void MMU_InvalidateIDCache(void);
/*
;void MMU_InvalidateIDCache(void)
EXPORT MMU_InvalidateIDCache
MMU_InvalidateIDCache
mov r0,#0x0
mcr p15,0,r0,c7,c7,0
MOV_PC_LR
*/
void MMU_InvalidateICache(void);
/*
;void MMU_InvalidateICache(void)
EXPORT MMU_InvalidateICache
MMU_InvalidateICache
mov r0,#0x0
mcr p15,0,r0,c7,c5,0
MOV_PC_LR
*/
void MMU_InvalidateICacheMVA(unsigned int mva);
/*
;void MMU_InvalidateICacheMVA(unsigned int mva)
EXPORT MMU_InvalidateICacheMVA
MMU_InvalidateICacheMVA
;r0=mva
mcr p15,0,r0,c7,c5,1
MOV_PC_LR
*/
void MMU_InvalidateICacheSET(unsigned int set);
/*
;void MMU_InvalidateICacheSET(unsigned int set)
EXPORT MMU_InvalidateICacheSET
MMU_InvalidateICacheSET
;r0=set/way
mcr p15,0,r0,c7,c5,2
MOV_PC_LR
*/
void MMU_PrefetchICacheMVA(unsigned int mva);
/*
;void MMU_PrefetchICacheMVA(unsigned int mva)
EXPORT MMU_PrefetchICacheMVA
MMU_PrefetchICacheMVA
;r0=mva
mcr p15,0,r0,c7,c13,1
MOV_PC_LR
*/
void MMU_InvalidateDCache(void);
/*
;void MMU_InvalidateDCache(void)
EXPORT MMU_InvalidateDCache
MMU_InvalidateDCache
mov r0,#0x0
mcr p15,0,r0,c7,c6,0
MOV_PC_LR
*/
void MMU_InvalidateDCacheMVA(unsigned int mva);
/*
;void MMU_InvalidateDCacheMVA(unsigned int mva)
EXPORT MMU_InvalidateDCacheMVA
MMU_InvalidateDCacheMVA
;r0=mva
mcr p15,0,r0,c7,c6,1
MOV_PC_LR
*/
void MMU_InvalidateDCacheSET(unsigned int set);
/*
;void MMU_InvalidateDCacheSET(unsigned int set)
EXPORT MMU_InvalidateDCacheSET
MMU_InvalidateDCacheSET
;r0=set/way
mcr p15,0,r0,c7,c6,2
MOV_PC_LR
*/
void MMU_CleanDCacheMVA(unsigned int mva);
/*
;void MMU_CleanDCacheMVA(unsigned int mva)
EXPORT MMU_CleanDCacheMVA
MMU_CleanDCacheMVA
;r0=mva
mcr p15,0,r0,c7,c10,1
MOV_PC_LR
*/
void MMU_CleanDCacheSET(unsigned int set);
/*
;void MMU_CleanDCacheSET(unsigned int set)
EXPORT MMU_CleanDCacheSET
MMU_CleanDCacheSET
;r0=set/way
mcr p15,0,r0,c7,c10,2
MOV_PC_LR
*/
void MMU_TestCleanDCache(void);
/*
;void MMU_TestCleanDCache(void)
EXPORT MMU_TestCleanDCache
MMU_TestCleanDCache
mrc p15,0,r0,c7,c10,3
MOV_PC_LR
*/
void MMU_CleanInvalidateDCacheMVA(unsigned int mva);
/*
;void MMU_CleanInvalidateDCacheMVA(unsigned int mva)
EXPORT MMU_CleanInvalidateDCacheMVA
MMU_CleanInvalidateDCacheMVA
;r0=mva
mcr p15,0,r0,c7,c14,1
MOV_PC_LR
*/
void MMU_CleanInvalidateDCacheSET(unsigned int set);
/*
;void MMU_CleanInvalidateDCacheSET(unsigned int set)
EXPORT MMU_CleanInvalidateDCacheSET
MMU_CleanInvalidateDCacheSET
;r0=set/way
mcr p15,0,r0,c7,c14,2
MOV_PC_LR
*/
void MMU_TestCleanInvalidateDCache(void) ;
/*
;void MMU_TestCleanInvalidateDCache(unsigned int index)
EXPORT MMU_TestCleanInvalidateDCache
MMU_TestCleanInvalidateDCache
mrc p15,0,r0,c7,c14,3
MOV_PC_LR
*/
void MMU_DrainWriteBuffer(void);
/*
;void MMU_DrainWriteBuffer(void)
EXPORT MMU_DrainWriteBuffer
MMU_DrainWriteBuffer
mov r0,#0x0
mcr p15,0,r0,c7,c10,4
MOV_PC_LR
*/
void MMU_WaitForInterrupt(void);
/*
;void MMU_WaitForInterrupt(void)
EXPORT MMU_WaitForInterrupt
MMU_WaitForInterrupt
mov r0,#0x0
mcr p15,0,r0,c7,c0,4
MOV_PC_LR
*/
void MMU_InvalidateTLB(void);
/*
;void MMU_InvalidateTLB(void)
;void MMU_InvalidateSetAssociativeTLB(void);ARM926EJ-S
EXPORT MMU_InvalidateTLB
MMU_InvalidateTLB
mov r0,#0x0
mcr p15,0,r0,c8,c7,0
MOV_PC_LR
*/
void MMU_InvalidateTLBMVA(unsigned int mva);
/*
;void MMU_InvalidateTLBMVA(unsigned int mva)
;void MMU_InvalidateTLBSingleEntry(unsigned int mva);ARM926EJ-S
EXPORT MMU_InvalidateTLBMVA
MMU_InvalidateTLBMVA
;r0=mva
mcr p15,0,r0,c8,c7,1
MOV_PC_LR
*/
void MMU_InvalidateITLB(void);
/*
;void MMU_InvalidateITLB(void)
;void MMU_InvalidateSetAssociativeTLB(void);ARM926EJ-S
EXPORT MMU_InvalidateITLB
MMU_InvalidateITLB
mcr p15,0,r0,c8,c5,0
MOV_PC_LR
*/
void MMU_InvalidateITLBMVA(unsigned int mva);
/*
;void MMU_InvalidateITLBMVA(unsigned int mva)
;void MMU_InvalidateTLBSingleEntry(unsigned int mva);ARM926EJ-S
EXPORT MMU_InvalidateITLBMVA
MMU_InvalidateITLBMVA
;r0=mva
mcr p15,0,r0,c8,c5,1
MOV_PC_LR
*/
void MMU_InvalidateDTLB(void);
/*
;void MMU_InvalidateDTLB(void)
;void MMU_InvalidateSetAssociativeTLB(void);ARM926EJ-S
EXPORT MMU_InvalidateDTLB
MMU_InvalidateDTLB
mov r0,#0x0
mcr p15,0,r0,c8,c6,0
MOV_PC_LR
*/
void MMU_InvalidateDTLBMVA(unsigned int mva);
/*
;void MMU_InvalidateDTLBMVA(unsigned int mva)
;void MMU_InvalidateTLBSingleEntry(unsigned int mva);ARM926EJ-S
EXPORT MMU_InvalidateDTLBMVA
MMU_InvalidateDTLBMVA
;r0=mva
mcr p15,0,r0,c8,c6,1
MOV_PC_LR
*/
void MMU_SetDCacheLockdownWay(unsigned int way);
/*
;void MMU_SetDCacheLockdownWay(unsigned int way)
EXPORT MMU_SetDCacheLockdownWay
MMU_SetDCacheLockdownWay
;r0= way to be lockdown
mrc p15,0,r1,c9,c0,0
orr r1, r1, r0
mcr p15,0,r1,c9,c0,0
MOV_PC_LR
*/
void MMU_SetDCacheUnlockdownWay(unsigned int way);
/*
;void MMU_SetDCacheUnlockdownWay(unsigned int way)
EXPORT MMU_SetDCacheUnlockdownWay
MMU_SetDCacheUnlockdownWay
;r0= way to be unlockdown
mrc p15,0,r1,c9,c0,0
bic r1, r1, r0
mcr p15,0,r1,c9,c0,0
MOV_PC_LR
*/
void MMU_SetICacheLockdownWay(unsigned int way);
/*
;void MMU_SetICacheLockdownWay(unsigned int way)
EXPORT MMU_SetICacheLockdownWay
MMU_SetICacheLockdownWay
;r0= way to be lockdown
mrc p15,0,r1,c9,c0,1
orr r1, r1, r0
mcr p15,0,r1,c9,c0,1
MOV_PC_LR
*/
void MMU_SetICacheUnlockdownWay(unsigned int way);
/*
;void MMU_SetICacheUnlockdownWay(unsigned int way)
EXPORT MMU_SetICacheUnlockdownWay
MMU_SetICacheUnlockdownWay
;r0= way to be unlockdown
mrc p15,0,r1,c9,c0,1
bic r1, r1, r0
mcr p15,0,r1,c9,c0,1
MOV_PC_LR
*/
void MMU_SetDTLBLockdown(unsigned int addr);
/*
;void MMU_SetDTLBLockdown(unsigned int addr)
EXPORT MMU_SetDTLBLockdown
MMU_SetDTLBLockdown
;r0= the address to be locked down
mov r1,r0 ; set r1 to the value of the address to be locked down
mcr p15,0,r1,c8,c7,1 ; invalidate TLB single entry to ensure that addr is not already in the TLB
mrc p15,0,r0,c10,c0,0 ; read the lockdown register
orr r0,r0,#1 ; set the preserve bit
mcr p15,0,r0,c10,c0,0 ; write to the lockdown register
ldr r1,[r1] ; TLB will miss, and entry will be loaded
mrc p15,0,r0,c10,c0,0 ; read the lockdown register (victim will have incremented)
bic r0,r0,#1 ; clear preserve bit
mcr p15,0,r0,c10,c0,0 ; write to the lockdown register
MOV_PC_LR
*/
void MMU_SetProcessId(unsigned int pid);
/*
;void MMU_SetProcessId(unsigned int pid)
EXPORT MMU_SetProcessId
MMU_SetProcessId
;r0= pid
mcr p15,0,r0,c13,c0,0
MOV_PC_LR
*/
int MMU_DebugRead(void);
/*
EXPORT MMU_DebugRead
MMU_DebugRead
;r0= value
mrc p15,0,r0,c15,c0,0
MOV_PC_LR
*/
void MMU_DebugWrite(unsigned int value);
/*
EXPORT MMU_DebugWrite
MMU_DebugWrite
;r0= value
mrc p15,0,r1,c15,c0,0
orr r1, r1, r0
mcr p15,0,r1,c15,c0,0
MOV_PC_LR
*/
void IsrIRQ( void);
/*
EXPORT IsrIRQ
IsrIRQ
sub sp,sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r9,=INTOFFSET
ldr r9,[r9]
ldr r8,= _ISR_STARTADDRESS + 0x20
add r8,r8,r9,lsl #2
ldr r8,[r8]
str r8,[sp,#8]
ldmfd sp!,{r8-r9,pc}
*/
#define DESC_SEC ((1<<1)|(1<<4))
#define CB (3<<2) //cache_on, write_back
#define CNB (2<<2) //cache_on, write_through
#define NCB (1<<2) //cache_off,WR_BUF on
#define NCNB (0<<2) //cache_off,WR_BUF off
#define AP_RW (3<<10) //supervisor=RW, user=RW
#define AP_RO (2<<10) //supervisor=RW, user=RO
#define AP_NO (1<<10) //supervisor=RW, user=No access
#define DOMAIN_FAULT (0x0)
#define DOMAIN_CHK (0x1)
#define DOMAIN_NOTCHK (0x3)
#define DOMAIN0 (0x0<<5)
#define DOMAIN1 (0x1<<5)
#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC)
#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC)
#define RW_NCB (AP_RW|DOMAIN0|NCB|DESC_SEC)
#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC)
#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC)
void MMU_Init(void);
void MMU_SetMTT(unsigned int vaddrStart,unsigned int vaddrEnd,unsigned int paddrStart,unsigned int attr);
void ChangeRomCacheStatus(int attr);
#ifdef __cplusplus
}
#endif
#endif /*__MMUCACHE_H__*/
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