Constraints file: mvbif.pcfLoading device database for application Par from file "mvbif_map.ncd".   "mvbif" is an NCD, version 2.38, device xc2s300e, package pq208, speed -6Loading device for application Par from file '2s300e.nph' in environment
C:/Xilinx.Device speed data version:  PRODUCTION 1.17 2003-06-19.Device utilization summary:   Number of External GCLKIOBs         1 out of 4      25%   Number of External IOBs            70 out of 142    49%      Number of LOCed External IOBs    0 out of 70      0%   Number of SLICEs                    5 out of 3072    1%   Number of GCLKs                     1 out of 4      25%Overall effort level (-ol):   Standard (set by user)Placer effort level (-pl):    Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl):    Standard (set by user)Phase 1.1Phase 1.1 (Checksum:9897b3) REAL time: 2 secs Phase 2.23Phase 2.23 (Checksum:1312cfe) REAL time: 2 secs Phase 3.3Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 2 secs Phase 5.8.Phase 5.8 (Checksum:9aa2e9) REAL time: 2 secs Phase 6.5Phase 6.5 (Checksum:39386fa) REAL time: 2 secs Phase 7.18Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs Writing design to file mvbif.ncd.Total REAL time to Placer completion: 2 secs Total CPU time to Placer completion: 1 secs Phase 1: 83 unrouted;       REAL time: 2 secs Phase 2: 52 unrouted;       REAL time: 2 secs Phase 3: 3 unrouted;       REAL time: 2 secs Phase 4: 0 unrouted;       REAL time: 2 secs Total REAL time to Router completion: 2 secs Total CPU time to Router completion: 1 secs Generating "par" statistics.**************************Generating Clock Report**************************+----------------------------+----------+--------+------------+-------------+|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|+----------------------------+----------+--------+------------+-------------+|         clk_BUFGP          |  Global  |   31   |  0.212     |  0.657      |+----------------------------+----------+--------+------------+-------------+   The Delay Summary Report   The SCORE FOR THIS DESIGN is: 187The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0   The AVERAGE CONNECTION DELAY for this design is:        1.285   The MAXIMUM PIN DELAY IS:                               4.353   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.903   Listing Pin Delays by value: (nsec)    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00   ---------   ---------   ---------   ---------   ---------   ---------          49          12          16           5           1           0Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 3 secs Total CPU time to PAR completion: 2 secs Peak Memory Usage:  57 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file mvbif.ncd.PAR done.