Release 6.1i - xst G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 1.16 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 1.16 s | Elapsed : 0.00 / 1.00 s --> Reading design: mvbif.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis     4.1) HDL Synthesis Report  5) Advanced HDL Synthesis  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : mvbif.prjInput Format                       : mixedIgnore Synthesis Constraint File   : NOVerilog Include Directory          : ---- Target ParametersOutput File Name                   : mvbifOutput Format                      : NGCTarget Device                      : xc2s300e-6-pq208---- Source OptionsTop Module Name                    : mvbifAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : lutAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 100Add Generic Clock Buffer(BUFG)     : 4Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : _Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : mvbif.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESOptimize Instantiated Primitives   : NO=========================================================================WARNING:Xst:1885 - LSO file is empty, default list of libraries is used=========================================================================*                          HDL Compilation                              *=========================================================================Compiling source file "mvbif.v"Module <mvbif> compiledNo errors in compilationAnalysis of file <mvbif.prj> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <mvbif>.Module <mvbif> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <mvbif>.    Related source file is mvbif.v.WARNING:Xst:647 - Input <rdy2mvbc_n> is never used.    Found 24-bit register for signal <addr_mvbc>.    Found 1-bit register for signal <wr_mvbc_n>.    Found 1-bit register for signal <rdy2cpu_n>.    Found 1-bit register for signal <rd_mvbc_n>.    Found 1-bit register for signal <cs_mvbc_n>.    Found 2-bit up counter for signal <counter>.    Found 1-bit register for signal <Delay>.    Summary:	inferred   1 Counter(s).	inferred  29 D-type flip-flop(s).Unit <mvbif> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers                        : 6  1-bit register                   : 5  24-bit register                  : 1# Counters                         : 1  2-bit up counter                 : 1==================================================================================================================================================*                       Advanced HDL Synthesis                          *==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <mvbif> ...Loading device for application Xst from file '2s300e.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block mvbif, actual ratio is 0.=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : mvbif.ngrTop Level Output File Name         : mvbifOutput Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : NODesign Statistics# IOs                              : 72Macro Statistics :# Registers                        : 5#      1-bit register              : 4#      24-bit register             : 1Cell Usage :# BELS                             : 5#      GND                         : 1#      LUT2                        : 2#      LUT4                        : 2# FlipFlops/Latches                : 28#      FD                          : 27#      FDS                         : 1# Clock Buffers                    : 1#      BUFGP                       : 1# IO Buffers                       : 70#      IBUF                        : 37#      OBUF                        : 33=========================================================================Device utilization summary:---------------------------Selected Device : 2s300epq208-6  Number of Slices:                      17  out of   3072     0%   Number of Slice Flip Flops:            28  out of   6144     0%   Number of 4 input LUTs:                 4  out of   6144     0%   Number of bonded IOBs:                 70  out of    146    47%   Number of GCLKs:                        1  out of      4    25%  =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT      GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+clk                                | BUFGP                  | 28    |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6   Minimum period: No path found   Minimum input arrival time before clock: 4.082ns   Maximum output required time after clock: 6.514ns   Maximum combinational path delay: 9.495nsTiming Detail:--------------All values displayed in nanoseconds (ns)-------------------------------------------------------------------------Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'Offset:              4.082ns (Levels of Logic = 2)  Source:            cs_cpu_n (PAD)  Destination:       rdy2cpu_n (FF)  Destination Clock: clk rising  Data Path: cs_cpu_n to rdy2cpu_n                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     IBUF:I->O             3   0.797   1.320  cs_cpu_n_IBUF (cs_cpu_n_IBUF)     LUT2:I0->O            1   0.468   0.920  _n00001 (_n0000)     FDS:S                     0.577          rdy2cpu_n    ----------------------------------------    Total                      4.082ns (1.842ns logic, 2.240ns route)                                       (45.1% logic, 54.9% route)-------------------------------------------------------------------------Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'Offset:              6.514ns (Levels of Logic = 1)  Source:            wr_mvbc_n (FF)  Destination:       wr_mvbc_n (PAD)  Source Clock:      clk rising  Data Path: wr_mvbc_n to wr_mvbc_n                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FD:C->Q               1   0.992   0.920  wr_mvbc_n (wr_mvbc_n_OBUF)     OBUF:I->O                 4.602          wr_mvbc_n_OBUF (wr_mvbc_n)    ----------------------------------------    Total                      6.514ns (5.594ns logic, 0.920ns route)                                       (85.9% logic, 14.1% route)-------------------------------------------------------------------------Timing constraint: Default path analysisDelay:               9.495ns (Levels of Logic = 4)  Source:            cs_cpu_n (PAD)  Destination:       SPARE0 (PAD)  Data Path: cs_cpu_n to SPARE0                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     IBUF:I->O             3   0.797   1.320  cs_cpu_n_IBUF (cs_cpu_n_IBUF)     LUT4:I3->O            1   0.468   0.920  SPARE09 (CHOICE19)     LUT2:I1->O            1   0.468   0.920  SPARE010 (SPARE0_OBUF)     OBUF:I->O                 4.602          SPARE0_OBUF (SPARE0)    ----------------------------------------    Total                      9.495ns (6.335ns logic, 3.160ns route)                                       (66.7% logic, 33.3% route)=========================================================================CPU : 3.89 / 5.55 s | Elapsed : 4.00 / 6.00 s --> Total memory usage is 61228 kilobytes