library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity jtd is
generic(n:integer:=1);
port(clk_n:in std_logic;
s:in std_logic_vector(1 downto 0);
th1,tl1,th2,tl2:out std_logic_vector(3 downto 0);
gry1,gry2:out std_logic_vector(2 downto 0)); 
end jtd;

architecture one of jtd is
type state1 is(green,yellow,red);
type state2 is(red,green,yellow);
signal clk:std_logic;
signal grya,gryb:std_logic_vector(2 downto 0);
begin 
p1:process(clk_n)
variable cnt:integer range 0 to n;
begin
if(clk_n'event and clk_n='1')then
if(cnt cnt:=cnt+1;
clk<='0';
else
cnt:=0;
clk<='1';
end if;
end if;
end process; 
p2:process(clk)
variable reset:std_logic;
variable th,tl:std_logic_vector(3 downto 0);
variable s1:state1;
begin
if(clk'event and clk='1')then
if(s="11" or s="00")then
case s1 is
when green=>if(reset='0')then
th:="0010";
tl:="0100";
reset:='1';
gry1<="010";
else
if not(th="0000" and tl="0001")then
if(tl="0000")then
tl:="1001";
th:=th-1; 
else
tl:=tl-1; 
end if;
else
th:="0000";
tl:="0000";
reset:='0';
s1:=red;
end if;
end if;
when red=>if(reset='0')then
th:="0001";
tl:="1001";
gry1<="100";
else
if not(th="0000" and tl="0001")then
if(tl="0000")then
tl:="1001";
th:=th-1; 
else
tl:=tl-1; 
end if;
else
th:="0000";
tl:="0000";
reset:='0';
s1:=yellow;
end if;
end if;
when yellow=>if(reset='0')then
th:="0000";
tl:="0100";
reset:='1';
gry1<="001";
else
if not(th="0000" and tl="0001")then
if(tl="0000")then
tl:="1001";
th:=th-1;
else
tl:=tl-1;
end if;
else
th:="0000";
tl:="0000";
reset:='0';
s1:=green;
end if;
end if;
end case;
else

if(s="10")then
if not(tl="0000")then
tl:=tl-1;
gry1<="001";
th:="0000";
else
gry1<="010";
th:="0000";
end if;
end if;
end if;
end if;
th1<=th;
tl1<=tl;
end process;
p3:process(clk)
variable reset:std_logic;
variable th,tl:std_logic_vector(3 downto 0);
variable s2:state2;
begin
if(clk'event and clk='1')then
if(s="00" or s="11")then
case s2 is
when green=>if(reset='0')then
th:="0010";
tl:="0100";
reset:='1';
gry2<="010";
else
if not(th="0000" and tl="0001")then
if(tl="0000")then
tl:="1001";
th:=th-1; 
else
tl:=tl-1; 
end if;
else
th:="0000";
tl:="0000";
reset:='0';
s2:=red;
end if;
end if;
when red=>if(reset='0')then
th:="0001";
tl:="1001";
reset:='1';
gry2<="100";
else
if not(th="0000" and tl="0001")then
if(tl="0000")then
tl:="1001";
th:=th-1; 
else
tl:=tl-1; 
end if;
else
th:="0000";
tl:="0000";
reset:='0';
s2:=yellow;
end if;
end if;
when yellow=>if(reset='0')then
th:="0000";
tl:="0100";
reset:='1';
gry2<="001";
else
if not(th="0000" and tl="0001")then
if(tl="0000")then
tl:="1001";
th:=th-1;
else
tl:=tl-1;
end if;
else
th:="0000";
tl:="0000";
reset:='0';
s2:=green;
end if;
end if;
end case;
else

if not(tl="0000")then
tl:=tl-1;
gry2<="001";
th:="0000";
else
gry2<="100";
th:="0000";
end if;
end if;

end if;
th2<=th;
tl2<=tl;
end process;
end one;