;/*
;**********************************************************************************************************
;*                                               
;*		    						S3C44BOX ARM7TDMI MotherBoard                                          
;*                                        
;*                              (c) Copyright 2003-2015, Zhang Zhi-gang
;*                                          All Rights Reserved
;*          
;*                               S3C44BOX Initialization Program for 1.0
;*
;* File  Name 	: INTDEF.S
;* By    Write	: Zhang Zhi-gang ( Barry Zhang )
;* First Write	: 2003-7-23 8:58
;* Last  Write	: 2003-7-23 9:21
;* where Write	: Room B201 Shenzhen International Tech-innovation Academy, Kejinan 10 Road ,
;*			  	  High-Tech Industrial Park,Shenzhen,China.
;* Function		: Define Interrupt
;*					1. Initialize Interrupt Name 			
;*					2. 								
;*					3. 
;**********************************************************************************************************
;*/

;/*
;**********************************************************************************************************
;*							Define the Mode of the CPU
;*
;*
;**********************************************************************************************************
;*/

INTLOCK         EQU     0xC0                 ;// Interrupt lockout value     
LOCK_MSK        EQU     0xC0                 ;// Interrupt lockout mask value
MODE_MASK       EQU     0x1F                 ;// Processor Mode Mask

MODE_USR		EQU		0x10
MODE_FIQ    	EQU     0x11                 
MODE_IRQ		EQU		0x12
MODE_SUP		EQU		0x13
MODE_ABT		EQU		0x17
MODE_UNDEF		EQU		0x1B
MODE_SYS		EQU		0x1F

I_BIT           EQU     0x80                 ;// Interrupt bit of CPSR and SPSR
F_BIT           EQU     0x40                 ;// Interrupt bit of CPSR and SPSR

;/*
;**********************************************************************************************************
;*										BUS WIDTH CONFIG
;* Buswidth: 16,32
;*
;**********************************************************************************************************
;*/
       ; GBLA    		BUSWIDTH
;BUSWIDTH		SETA    16

;/*
;**********************************************************************************************************
;*											INTERRUPT DEFINE					
;*
;*
;**********************************************************************************************************
;*/
STACK_LIMIT				EQU			0X37FDA7E0
SYS_STACK				EQU			STACK_LIMIT	
SVC_STACK				EQU			SYS_STACK - 0x2000
IRQ_STACK				EQU			SVC_STACK - 0x2000
;//SVC_Stack_Size		EQU			1024
;//IRQ_STACK_SIZE		EQU			1024
;//FIQ_STACK_SIZE		EQU			1024

;/*********************************************************************************************************
;*  									INTERRUPT VECTOR DEFINES
;*        
;* 			Defines for the vector numbers associated with each interrupt.  The vector     
;* 			is determined by the bit position of the interrupt in the IRQ pending register
;**********************************************************************************************************
;*/               	    		
Handler_EINT0		EQU			0
Handler_EINT1		EQU			1
Handler_EINT2		EQU			2
Handler_EINT3		EQU			3
        	    		
Handler_EINT4_7		EQU			4
Handler_EINT8_23	EQU			5
Handler_nBATT_FLT	EQU			7
Handler_TICK		EQU			8
Handler_WDT			EQU			9
Handler_TIMER0		EQU			10
Handler_TIMER1		EQU			11
Handler_TIMER2		EQU			12
Handler_TIMER3		EQU			13
Handler_TIMER4		EQU			14
Handler_UART2		EQU			15
Handler_LCD			EQU			16
Handler_DMA0		EQU			17
Handler_DMA1		EQU			18
Handler_DMA2		EQU			19
Handler_DMA3		EQU			20
Handler_SDI			EQU			21
Handler_SPI0		EQU			22
Handler_UART1		EQU			23
Handler_USBD		EQU			25
Handler_USBH		EQU			26
Handler_IIC			EQU			27
Handler_UART0		EQU			28
Handler_SPI1		EQU			29
Handler_RTC			EQU			30
Handler_ADC			EQU			31



;/*********************************************************************************************************/	

	END