/*****************************************************************************
*
* Motorola Inc.
* (c) Copyright 2000 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
******************************************************************************
*
* File Name: config.c
*
* Description: initialization code
*
* Modules Included:
*
*****************************************************************************/

#include "appconfig.h"

extern void Start(void);

extern void main(void);

asm    void configInterruptVector(void);
       void configUnhandledInterruptISR(void);
extern void userPostMain(void);
extern void userPreMain(void);

/*****************************************************************************
    configInterruptVector - Interrupt Vector Table
	The following Interrupt Vector MUST be at the beginning of this
	config.c file so that it is located at P:0x0000 by the linker.cmd file.
*****************************************************************************/
asm void configInterruptVector(void)
{
		jsr	  Start							/* Hardware Reset */
		

	#ifdef INT_VECTOR_ADDR_1			/* COP Watchdog Reset */
		jsr   INT_VECTOR_ADDR_1
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_2			/* Reserved */
		jsr   INT_VECTOR_ADDR_2
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_3			/* Illegal Instruction */
		jsr   INT_VECTOR_ADDR_3
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_4			/* SWI */
		jsr   INT_VECTOR_ADDR_4
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_5			/* HW Stack Overflow */
		jsr   INT_VECTOR_ADDR_5
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_6			/* OnCE Trap */
		jsr   INT_VECTOR_ADDR_6
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_7			/* Reserved */
		jsr   INT_VECTOR_ADDR_7
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_8			/* IRQA */
		jsr   INT_VECTOR_ADDR_8
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_9			/* IRQB */
		jsr   INT_VECTOR_ADDR_9
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_10			/* Reserved */
		jsr   INT_VECTOR_ADDR_10
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_11			/* Boot Flash Interface */
		jsr   INT_VECTOR_ADDR_11
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_12			/* Program Flash Interface */
		jsr   INT_VECTOR_ADDR_12
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_13			/* Data Flash Interface */
		jsr   INT_VECTOR_ADDR_13
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_14			/* MSCAN Transmitter Ready */
		jsr   INT_VECTOR_ADDR_14
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_15			/* MSCAN Receiver Ready */
		jsr   INT_VECTOR_ADDR_15
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_16			/* MSCAN Error */
		jsr   INT_VECTOR_ADDR_16
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_17			/* MSCAN Wakeup */
		jsr   INT_VECTOR_ADDR_17
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_18			/* Reserved */
		jsr   INT_VECTOR_ADDR_18
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_19			/* GPIO E */
		jsr   INT_VECTOR_ADDR_19
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_20			/* GPIO D */
		jsr   INT_VECTOR_ADDR_20
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_21			/* Reserved */
		jsr   INT_VECTOR_ADDR_21
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_22			/* GPIO B */
		jsr   INT_VECTOR_ADDR_22
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_23			/* GPIO A */
		jsr   INT_VECTOR_ADDR_23
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_24			/* SPI Transmitter Empty */
		jsr   INT_VECTOR_ADDR_24
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_25			/* SPI Receiver Full and/or Error */
		jsr   INT_VECTOR_ADDR_25
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_26			/* Quadrature Decoder #1 Home switch or Watchdog */
		jsr   INT_VECTOR_ADDR_26
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_27			/* Quadrature Decoder #1 INDEX Pulse */
		jsr   INT_VECTOR_ADDR_27
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_28			/* Quadrature Decoder #0 Home switch or Watchdog */
		jsr   INT_VECTOR_ADDR_28
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_29			/* Quadrature Decoder #0 INDEX Pulse */
		jsr   INT_VECTOR_ADDR_29
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_30			/* Timer D Channel 0 */
		jsr   INT_VECTOR_ADDR_30
	#else
		jsr   configUnhandledInterruptISR
	#endif
	
	#ifdef INT_VECTOR_ADDR_31			/* Timer D Channel 1 */
		jsr   INT_VECTOR_ADDR_31
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_32			/* Timer D Channel 2 */
		jsr   INT_VECTOR_ADDR_32
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_33			/* Timer D Channel 3 */
		jsr   INT_VECTOR_ADDR_33
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_34			/* Timer C Channel 0 */
		jsr   INT_VECTOR_ADDR_34
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_35			/* Timer C Channel 1 */
		jsr   INT_VECTOR_ADDR_35
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_36			/* Timer C Channel 2 */
		jsr   INT_VECTOR_ADDR_36
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_37			/* Timer C Channel 3 */
		jsr   INT_VECTOR_ADDR_37
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_38			/* Timer B Channel 0 */
		jsr   INT_VECTOR_ADDR_38
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_39			/* Timer B Channel 1 */
		jsr   INT_VECTOR_ADDR_39
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_40			/* Timer B Channel 2 */
		jsr   INT_VECTOR_ADDR_40
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_41			/* Timer B Channel 3 */
		jsr   INT_VECTOR_ADDR_41
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_42			/* Timer A Channel 0 */
		jsr   INT_VECTOR_ADDR_42
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_43			/* Timer A Channel 1 */
		jsr   INT_VECTOR_ADDR_43
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_44			/* Timer A Channel 2 */
		jsr   INT_VECTOR_ADDR_44
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_45			/* Timer A Channel 3 */
		jsr   INT_VECTOR_ADDR_45
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_46			/* SCI #1 Transmit Complete */
		jsr   INT_VECTOR_ADDR_46
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_47			/* SCI #1 Transmitter Ready */
		jsr   INT_VECTOR_ADDR_47
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_48			/* SCI #1 Receiver Error */
		jsr   INT_VECTOR_ADDR_48
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_49			/* SCI #1 Receiver Full */
		jsr   INT_VECTOR_ADDR_49
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_50			/* SCI #0 Transmit Complete */
		jsr   INT_VECTOR_ADDR_50
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_51			/* SCI #0 Transmitter Ready */
		jsr   INT_VECTOR_ADDR_51
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_52			/* SCI #0 Receiver Error */
		jsr   INT_VECTOR_ADDR_52
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_53			/* SCI #0 Receiver Full */
		jsr   INT_VECTOR_ADDR_53
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_54			/* ADC B Conversion Complete */
		jsr   INT_VECTOR_ADDR_54
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_55			/* ADC A Conversion Complete */
		jsr   INT_VECTOR_ADDR_55
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_56			/* ADC B Zero Crossing or Limit Error */
		jsr   INT_VECTOR_ADDR_56
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_57			/* ADC A Zero Crossing or Limit Error */
		jsr   INT_VECTOR_ADDR_57
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_58			/* Reload PWM B */
		jsr   INT_VECTOR_ADDR_58
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_59			/* Reload PWM A */
		jsr   INT_VECTOR_ADDR_59
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_60			/* PWM B Fault */
		jsr   INT_VECTOR_ADDR_60
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_61			/* PWM A Fault */
		jsr   INT_VECTOR_ADDR_61
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_62			/* PLL Loss of Lock */
		jsr   INT_VECTOR_ADDR_62
	#else
		jsr   configUnhandledInterruptISR
	#endif

	#ifdef INT_VECTOR_ADDR_63			/* Low Voltage Detector */
		jsr   INT_VECTOR_ADDR_63
	#else
		jsr   configUnhandledInterruptISR
	#endif
}



asm void configUnhandledInterruptISR(void)
{
	/* 
		No interrupt handler had been specified for the interrupt vector,
		so the interrupt vector defaulted to this routine where is 
		no code.
	*/
	debug
	rti
}