/* ============================================================================*/ 
/*          Copyright (C) 2004 YINXING TECHNOLOGY CO., LTD                     */ 
/*                          All Rights Reserved.                               */ 
/* ----------------------------------------------------------------------------*/ 
/* ============================================================================*/ 





 
MEMORY
{
    PAGE 0: IPROG:      origin = 0x3080,        len = 0x1F80
            VECT:       origin = 0x3000,        len = 0x80
            EPROG:      origin = 0x38000,       len = 0x8000

    PAGE 1: USERREGS:   origin = 0x60,          len = 0x1c
            BIOSREGS:   origin = 0x7c,          len = 0x4
            IDATA:      origin = 0x80,          len = 0xB80
            EDATA:      origin = 0xC00,        len = 0x1400
            
}

SECTIONS
{
    .vectors: {} > VECT PAGE 0
    .sysregs: {} > BIOSREGS PAGE 1
    .trcinit: {} > IPROG PAGE 0
    .gblinit: {} > IPROG PAGE 0
    .bios:    {} > IPROG PAGE 0
     frt:     {} > IPROG PAGE 0
    .text:    {} > IPROG PAGE 0
    .cinit:   {} > IPROG PAGE 0
    .pinit:   {} > IPROG PAGE 0
    .sysinit: {} > IPROG PAGE 0  
    .data     {} > EDATA PAGE 1
    .bss:     {} > IDATA PAGE 1
    .far:     {} > IDATA PAGE 1
    .const:   {} > IDATA PAGE 1
    .switch:  {} > IDATA PAGE 1
    .sysmem:  {} > IDATA PAGE 1
    .cio:     {} > IDATA PAGE 1
    .MEM$obj: {} > IDATA PAGE 1
    .sysheap: {} > IDATA PAGE 1
}