/* ppc405GP.h - IBM PowerPC 405GP Chip header */

/*******************************************************************************
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   licensors will be responsible for any consequences resulting from the use
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   COPYRIGHT   I B M   CORPORATION 2000
   LICENSED MATERIAL  -  PROGRAM PROPERTY OF  I B M"

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/* Copyright 1984-1999 Wind River Systems, Inc. */

/*
modification history
--------------------
01g,21jan02,jl   added cypress sl811hs daughter card support
01f,06dec00,s_m  added Rev E PVR
01e,26may00,mcg  moved DMA register information to its own header file
01d,15may00,mcg  register name updates to match 405GP User Manual
01c,18apr00,mcg  fix PCI_IO_REGION_X definitions
01b,15jan00,mcg  move MAL, UIC, SDRAM controller info to their own .h files
01a,09sep99,mcg  created
*/

/*
This file contains DCR (Device Control Register) addresses and other chip
specific information for the IBM PowerPC 405GP outside of the 405 processor
core (see ppc405.h for 405 processor core information).
*/

#ifndef INCppc405GPh
#define INCppc405GPh


/*
 * The 405GP chip uses the 405B3 processor core which has a 16KB I-cache and a
 * 8KB D-cache.  All 405 processor cores have 32 byte cache lines, and are
 * 2-way set associative.
 */

#define _ICACHE_LINE_NUM_405GP 256                     /* 256 * 32 * 2 = 16KB */
#define _DCACHE_LINE_NUM_405GP 128                     /* 128 * 32 * 2 =  8KB */


/*
 * Processor Version Register (PVR) values for 405GP
 */

#define PVR_405GP_RA    0x40110000        /* 405GP Revision A (not supported) */
#define PVR_405GP_RB    0x40110040        /* 405GP Revision B (not supported) */
#define PVR_405GP_RC    0x40110082        /* 405GP Revision C (not supported) */
#define PVR_405GP_RD    0x401100C4        /* 405GP Revision D                 */
#define PVR_405GP_RE    0x40110145        /* 405GP Revision E                 */

#define WRONG_CPU_MSG ".This version of the CPU is not supported\n";

/*
 * Reduce the number of MAL channel DCR access functions because a MAL with
 * only 8 channels is used in the 405GP.
 */

#define MAL_CHANNELS_8

/*
 * Valid Memory Access Layer (MAL) channels.  On the 405GP, EMAC is the only
 * communications core that uses MAL.  It has 2 TX channels, and 1 TX channel.
 */

#define MAL_CHN_TX_405GP  0xC0000000      /* TX channels 0 and 1              */
#define MAL_CHN_RX_405GP  0x80000000      /* RX channel  0                    */

/*
 * MAL channels numbers the EMAC Ethernet controller is connected to on 405GP.
 * This information is put into the EMAC driver END load string.
 */

#define EMAC_TX_CHN_0_405GP     0
#define EMAC_TX_CHN_1_405GP     1
#define EMAC_RX_CHN_0_405GP     0

/*
 * Base DCR address values for all perhipheral cores in the 405GP
 */

#define SDRAM_DCR_BASE        0x010       /* SDRAM Controller                 */
#define EBC_DCR_BASE          0x012       /* External Bus Controller          */
#define UIC_DCR_BASE          0x0C0       /* Universal Interrupt Controller   */
#define DMA_DCR_BASE          0x100       /* DMA Controller                   */
#define CLKPWRCH_DCR_BASE     0x0B0       /* Clock/Power/Chip Control         */
#define MAL_DCR_BASE          0x180       /* Memory Access Layer Core         */
#define DECOMP_DCR_BASE       0x014       /* Code Decompression Core          */
#define OCM_DCR_BASE          0x018       /* On-chip Memory Controller        */

/*
 * Static interrupt vectors/levels.  These also correspond to bit numbers in
 * many of the registers of the Universal Interrupt Controller.
 */
#define INT_VEC_UART0             0
#define INT_VEC_UART1             1
#define INT_VEC_IIC               2
#define INT_VEC_EXT_MASTER        3
#define INT_VEC_PCI               4
#define INT_VEC_DMA_CH0           5
#define INT_VEC_DMA_CH1           6
#define INT_VEC_DMA_CH2           7
#define INT_VEC_DMA_CH3           8
#define INT_VEC_ENET_WAKEUP       9
#define INT_VEC_MAL_SERR          10
#define INT_VEC_MAL_TXEOB         11
#define INT_VEC_MAL_RXEOB         12
#define INT_VEC_MAL_TXDE          13
#define INT_VEC_MAL_RXDE          14
#define INT_VEC_ETHERNET          15
#define INT_VEC_PCI_SERR          16
#define INT_VEC_TIMER             17
#define INT_VEC_EXT_IRQ_0         25
#define INT_VEC_EXT_IRQ_1         26
#define INT_VEC_EXT_IRQ_2         27
#define INT_VEC_EXT_IRQ_3         28
#define INT_VEC_EXT_IRQ_4         29
#define INT_VEC_EXT_IRQ_5         30
#define INT_VEC_EXT_IRQ_6         31

#define INT_LVL_UART0             0
#define INT_LVL_UART1             1
#define INT_LVL_IIC               2
#define INT_LVL_EXT_MASTER        3
#define INT_LVL_PCI               4
#define INT_LVL_DMA_CH0           5
#define INT_LVL_DMA_CH1           6
#define INT_LVL_DMA_CH2           7
#define INT_LVL_DMA_CH3           8
#define INT_LVL_ENET_WAKEUP       9
#define INT_LVL_MAL_SERR          10
#define INT_LVL_MAL_TXEOB         11
#define INT_LVL_MAL_RXEOB         12
#define INT_LVL_MAL_TXDE          13
#define INT_LVL_MAL_RXDE          14
#define INT_LVL_ETHERNET          15
#define INT_LVL_PCI_SERR          16
#define INT_LVL_TIMER             17
#define INT_LVL_EXT_IRQ_0         25
#define INT_LVL_EXT_IRQ_1         26
#define INT_LVL_EXT_IRQ_2         27
#define INT_LVL_EXT_IRQ_3         28
#define INT_LVL_EXT_IRQ_4         29
#define INT_LVL_EXT_IRQ_5         30
#define INT_LVL_EXT_IRQ_6         31

/*
 * Clock, power management, chip control and strapping register defintions.
 * Each is a separate DCR register.
 */
#define CPC0_PLLMR  (CLKPWRCH_DCR_BASE+0x0)  /* PLL Mode Register             */
#define CPC0_CR0    (CLKPWRCH_DCR_BASE+0x1)  /* Chip control 0 Register       */
#define CPC0_CR1    (CLKPWRCH_DCR_BASE+0x2)  /* Chip control 1 Register       */
#define CPC0_PSR    (CLKPWRCH_DCR_BASE+0x4)  /* Pin Strapping Register        */
#define CPC0_SR     (CLKPWRCH_DCR_BASE+0x8)  /* clock/power management status */
#define CPC0_ER     (CLKPWRCH_DCR_BASE+0x9)  /* clock/power management enable */
#define CPC0_FR     (CLKPWRCH_DCR_BASE+0xa)  /* clock/power management force  */

/* Bit definitions */
#define PLLMR_FWD_DIV_MASK      0xE0000000     /* Forward Divisor */
#define PLLMR_FWD_DIV_BYPASS    0xE0000000
#define PLLMR_FWD_DIV_3         0xA0000000
#define PLLMR_FWD_DIV_4         0x80000000
#define PLLMR_FWD_DIV_6         0x40000000

#define PLLMR_FB_DIV_MASK       0x1E000000     /* Feedback Divisor */
#define PLLMR_FB_DIV_1          0x02000000
#define PLLMR_FB_DIV_2          0x04000000
#define PLLMR_FB_DIV_3          0x06000000
#define PLLMR_FB_DIV_4          0x08000000

#define PLLMR_TUNING_MASK       0x01F80000

#define PLLMR_CPU_TO_PLB_MASK   0x00060000     /* CPU:PLB Frequency Divisor */
#define PLLMR_CPU_PLB_DIV_1     0x00000000
#define PLLMR_CPU_PLB_DIV_2     0x00020000
#define PLLMR_CPU_PLB_DIV_3     0x00040000
#define PLLMR_CPU_PLB_DIV_4     0x00060000

#define PLLMR_OPB_TO_PLB_MASK   0x00018000     /* OPB:PLB Frequency Divisor */
#define PLLMR_OPB_PLB_DIV_1     0x00000000
#define PLLMR_OPB_PLB_DIV_2     0x00008000
#define PLLMR_OPB_PLB_DIV_3     0x00010000
#define PLLMR_OPB_PLB_DIV_4     0x00018000

#define PLLMR_PCI_TO_PLB_MASK   0x00006000     /* PCI:PLB Frequency Divisor */
#define PLLMR_PCI_PLB_DIV_1     0x00000000
#define PLLMR_PCI_PLB_DIV_2     0x00002000
#define PLLMR_PCI_PLB_DIV_3     0x00004000
#define PLLMR_PCI_PLB_DIV_4     0x00006000

#define PLLMR_EXB_TO_PLB_MASK   0x00001800     /* External Bus:PLB Divisor  */
#define PLLMR_EXB_PLB_DIV_2     0x00000000
#define PLLMR_EXB_PLB_DIV_3     0x00000800
#define PLLMR_EXB_PLB_DIV_4     0x00001000
#define PLLMR_EXB_PLB_DIV_5     0x00001800

/*
 * PLL Voltage Controlled Oscillator (VCO) definitions
 * Maximum and minimum values (in MHz) for correct PLL operation.
 */
#define VCO_MIN     400
#define VCO_MAX     800

/* Chip Control Register 0 bits */
#define CR0_PLL_MODE_REG_EN     0x80000000
#define CR0_GPIO_10_EN          0x04000000
#define CR0_GPIO_11_EN          0x02000000
#define CR0_GPIO_12_EN          0x01000000
#define CR0_GPIO_13_EN          0x00800000
#define CR0_GPIO_14_EN          0x00400000
#define CR0_GPIO_15_EN          0x00200000
#define CR0_GPIO_16_EN          0x00100000
#define CR0_GPIO_17_EN          0x00080000
#define CR0_GPIO_18_EN          0x00040000
#define CR0_GPIO_19_EN          0x00020000
#define CR0_GPIO_20_EN          0x00010000
#define CR0_GPIO_21_EN          0x00008000
#define CR0_GPIO_22_EN          0x00004000
#define CR0_GPIO_23_EN          0x00002000
#define CR0_UART1_CTS_EN        0x00001000
#define CR0_UART1_DTR_EN        0x00000800
#define CR0_UART0_EXT_CLK       0x00000080
#define CR0_UART1_EXT_CLK       0x00000040
#define CR0_UART_DIV_MASK       0x0000003E


#define CR1_DET_MULT_EN         0x80000000
#define CR1_EXT_TIMER_EN        0x00800000
#define CR1_PCI_PW_EN           0x00004000

#define PSR_PLL_FWD_MASK        0xC0000000
#define PSR_PLL_FDBACK_MASK     0x30000000
#define PSR_PLL_TUNING_MASK     0x0E000000
#define PSR_PLB_CPU_MASK        0x01800000
#define PSR_OPB_PLB_MASK        0x00600000
#define PSR_PCI_PLB_MASK        0x00180000
#define PSR_EB_PLB_MASK         0x00060000
#define PSR_ROM_WIDTH_MASK      0x00018000
#define PSR_ROM_LOC             0x00004000
#define PSR_PCI_ASYNC_EN        0x00001000
#define PSR_PCI_ARBIT_EN        0x00000400

/*
 * On-chip memory controller configuration register definitions.
 */

#define OCM_ISARC  (OCM_DCR_BASE+0x00)    /* Instruction-side Addr range cmp  */
#define OCM_ISCNTL (OCM_DCR_BASE+0x01)    /* Instruction-side control reg     */
#define OCM_DSARC  (OCM_DCR_BASE+0x02)    /* Data-side Addr range cmp         */
#define OCM_DSCNTL (OCM_DCR_BASE+0x03)    /* Data-side control reg            */

/* OCM register bits */

#define OCM_DSAR    0xFC000000            /* OCM D-side address mask          */
#define OCM_DSEN    0x80000000            /* OCM D-side enable                */

#define OCM_ISAR    0xFC000000            /* OCM I-side address mask          */
#define OCM_ISEN    0x80000000            /* OCM I-side enable                */
#define OCM_ISTCM   0x40000000            /* OCM I-side 2 cycle mode          */


/*
 * CodePack Code Decompression core register definitions. Two DCRs are used
 * (address/data) to indirectly access the config registers of this controller.