?? mp3.lst
字號:
__start:
__text_start:
0158 EFCF LDI R28,0xFF
0159 E1D0 LDI R29,0x10
015A BFCD OUT 0x3D,R28
015B BFDE OUT 0x3E,R29
015C 58C0 SUBI R28,0x80
015D 40D0 SBCI R29,0
015E EA0A LDI R16,0xAA
015F 8308 STD Y+0,R16
0160 2400 CLR R0
0161 E2E0 LDI R30,0x20
0162 E0F2 LDI R31,2
0163 E016 LDI R17,6
0164 36EA CPI R30,0x6A
0165 07F1 CPC R31,R17
0166 F011 BEQ 0x0169
0167 9201 ST R0,Z+
0168 CFFB RJMP 0x0164
0169 8300 STD Z+0,R16
016A E8EF LDI R30,0x8F
016B E0F1 LDI R31,1
016C E0A0 LDI R26,0
016D E0B1 LDI R27,1
016E E012 LDI R17,2
016F 3AEF CPI R30,0xAF
0170 07F1 CPC R31,R17
0171 F021 BEQ 0x0176
0172 95C8 LPM
0173 9631 ADIW R30,1
0174 920D ST R0,X+
0175 CFF9 RJMP 0x016F
0176 940E081A CALL _main
_exit:
0178 CFFF RJMP _exit
_init_ata:
j --> Y+1
i --> Y+1
word_read --> Y+1
device --> R20
0179 940E15D7 CALL push_gset2
017B 2F40 MOV R20,R16
FILE: G:\IccPro\Mp3Ide\ata.c
(0001) #include <iom128v.h>
(0002) #include <string.h>
(0003) #include <stdio.h>
(0004) #include <macros.h>
(0005) #include "ata.h"
(0006) #include "generic.h"
(0007) #include "remote.h"
(0008)
(0009) #define debug
(0010) #define debugport 1
(0011)
(0012) //******************************************************************
(0013) //* INITIALIZE HARDWARE FOR ATA DRIVER
(0014) //*
(0015) //*
(0016) //******************************************************************
(0017) int init_ata(unsigned char device)
(0018) {
(0019) unsigned int word_read,i,j;
(0020)
(0021) ata_databus_in;
017C 2422 CLR R2
017D BA2A OUT 0x1A,R2
017E BA24 OUT 0x14,R2
(0022) PORT_ATA_IO_CNTL_DDR = 0xff;
017F EF8F LDI R24,0xFF
0180 93800061 STS 0x61,R24
(0023) PORT_ATA_IO_CNTL = ATA_IO_HIZ;
0182 93800062 STS 0x62,R24
(0024) PORT_ATA_RST_CNTL_DDR |= ATA_RESET;
0184 91800064 LDS R24,0x64
0186 6082 ORI R24,2
0187 93800064 STS 0x64,R24
(0025)
(0026) ata_hard_reset();
0189 D03D RCALL _ata_hard_reset
(0027)
(0028) while (!ready & busy);
018A D10E RCALL _ata_rdy
018B 2300 TST R16
018C F419 BNE 0x0190
018D E061 LDI R22,1
018E E070 LDI R23,0
018F C002 RJMP 0x0192
0190 2766 CLR R22
0191 2777 CLR R23
0192 D10E RCALL _ata_bsy
0193 2E20 MOV R2,R16
0194 2433 CLR R3
0195 012B MOVW R4,R22
0196 2042 AND R4,R2
0197 2053 AND R5,R3
0198 2044 TST R4
0199 F781 BNE 0x018A
019A 2055 TST R5
019B F771 BNE 0x018A
(0029) ata_select_device(device);
019C 2F04 MOV R16,R20
019D D03F RCALL _ata_select_device
(0030) while (!ready & busy);
019E D0FA RCALL _ata_rdy
019F 2300 TST R16
01A0 F419 BNE 0x01A4
01A1 E061 LDI R22,1
01A2 E070 LDI R23,0
01A3 C002 RJMP 0x01A6
01A4 2766 CLR R22
01A5 2777 CLR R23
01A6 D0FA RCALL _ata_bsy
01A7 2E20 MOV R2,R16
01A8 2433 CLR R3
01A9 012B MOVW R4,R22
01AA 2042 AND R4,R2
01AB 2053 AND R5,R3
01AC 2044 TST R4
01AD F781 BNE 0x019E
01AE 2055 TST R5
01AF F771 BNE 0x019E
(0031) ata_write_byte(ATA_IO_CMD,CMD_RECALIBRATE);
01B0 E120 LDI R18,0x10
01B1 EF0D LDI R16,0xFD
01B2 D085 RCALL _ata_write_byte
(0032) while (busy);
01B3 D0ED RCALL _ata_bsy
01B4 2300 TST R16
01B5 F7E9 BNE 0x01B3
(0033) ata_write_byte(ATA_IO_SECTORCNT,60); // Sleep after 5 min
01B6 E32C LDI R18,0x3C
01B7 EE05 LDI R16,0xE5
01B8 D07F RCALL _ata_write_byte
(0034) while (busy);
01B9 D0E7 RCALL _ata_bsy
01BA 2300 TST R16
01BB F7E9 BNE 0x01B9
(0035) ata_write_byte(ATA_IO_CMD,CMD_STANDBY2);
01BC E926 LDI R18,0x96
01BD EF0D LDI R16,0xFD
01BE D079 RCALL _ata_write_byte
(0036) while (busy);
01BF D0E1 RCALL _ata_bsy
01C0 2300 TST R16
01C1 F7E9 BNE 0x01BF
(0037)
(0038) return 1;
01C2 E001 LDI R16,1
01C3 E010 LDI R17,0
01C4 940E15C5 CALL pop_gset2
01C6 9508 RET
(0039) }
(0040)
(0041) //******************************************************************
(0042) //* PERFORM HARDWARE RESET
(0043) //* This routine toggles ATA RESET line low for 10ms.
(0044) //*
(0045) //******************************************************************
(0046) void ata_hard_reset(void)
(0047) {
(0048) ata_databus_in;
_ata_hard_reset:
01C7 2422 CLR R2
01C8 BA2A OUT 0x1A,R2
01C9 BA24 OUT 0x14,R2
(0049) PORT_ATA_RST_CNTL &= ~ATA_RESET;
01CA 91800065 LDS R24,0x65
01CC 7F8D ANDI R24,0xFD
01CD 93800065 STS 0x65,R24
(0050) delay_ms(10);
01CF E00A LDI R16,0xA
01D0 E010 LDI R17,0
01D1 940E07EE CALL _delay_ms
(0051) PORT_ATA_RST_CNTL |= ATA_RESET;
01D3 91800065 LDS R24,0x65
01D5 6082 ORI R24,2
01D6 93800065 STS 0x65,R24
(0052) delay_ms(10);
01D8 E00A LDI R16,0xA
01D9 E010 LDI R17,0
01DA 940E07EE CALL _delay_ms
01DC 9508 RET
_ata_select_device:
device --> R20
01DD 940E15D9 CALL push_gset1
01DF 2F40 MOV R20,R16
(0053) }
(0054)
(0055) //******************************************************************
(0056) //* SELECT ATA DEVICE
(0057) //* This routine defaults to Drive 0 as the target drive.
(0058) //*
(0059) //******************************************************************
(0060) void ata_select_device(unsigned char device)
(0061) {
(0062) switch (device)
01E0 2755 CLR R21
01E1 3040 CPI R20,0
01E2 0745 CPC R20,R21
01E3 F029 BEQ 0x01E9
01E4 3041 CPI R20,1
01E5 E0E0 LDI R30,0
01E6 075E CPC R21,R30
01E7 F029 BEQ 0x01ED
01E8 C008 RJMP 0x01F1
(0063) {
(0064) case 0x00:
(0065) ata_write_byte(ATA_IO_DEVICE_HEAD,ATA_DH_DEV0);
01E9 EE20 LDI R18,0xE0
01EA EF05 LDI R16,0xF5
01EB D04C RCALL _ata_write_byte
(0066) break;
01EC C007 RJMP 0x01F4
(0067) case 0x01:
(0068) ata_write_byte(ATA_IO_DEVICE_HEAD,ATA_DH_DEV1);
01ED EF20 LDI R18,0xF0
01EE EF05 LDI R16,0xF5
01EF D048 RCALL _ata_write_byte
(0069) break;
01F0 C003 RJMP 0x01F4
(0070) default:
(0071) ata_write_byte(ATA_IO_DEVICE_HEAD,ATA_DH_DEV0);
01F1 EE20 LDI R18,0xE0
01F2 EF05 LDI R16,0xF5
01F3 D044 RCALL _ata_write_byte
(0072) break;
01F4 940E15DC CALL pop_gset1
01F6 9508 RET
_ata_write_word:
wordout --> R20
reg --> R22
01F7 940E15D7 CALL push_gset2
01F9 01A9 MOVW R20,R18
01FA 2F60 MOV R22,R16
(0073) }
(0074) }
(0075)
(0076) //******************************************************************
(0077) //* WRITE WORD TO ATA DEVICE
(0078) //*
(0079) //* Mapping : D0-PA0,D1-PA2,D2-PA4,D3-PA6,D4-PC7,D5-PC5,D7-PC3,D7-PC1
(0080) //* D8-PC0,D9-PC2,D10-PC4,D11-PC6,D12-PA7,D13-PA5,D14-PA3,D15-PA1
(0081) //******************************************************************
(0082) void ata_write_word(unsigned char reg,unsigned int wordout)
(0083) {
(0084) WDR();
01FB 95A8 WDR
(0085) PORT_ATA_IO_CNTL = reg;
01FC 93600062 STS 0x62,R22
(0086)
(0087) ata_databus_out;
01FE EF8F LDI R24,0xFF
01FF BB8A OUT 0x1A,R24
0200 BB84 OUT 0x14,R24
(0088)
(0089) PORT_ATA_DATA1_OUT = 0x00;
0201 2422 CLR R2
0202 BA2B OUT 0x1B,R2
(0090) PORT_ATA_DATA2_OUT = 0x00;
0203 BA25 OUT 0x15,R2
(0091)
(0092) if (wordout & 0x0001) PORT_ATA_DATA1_OUT |= 0x01;
0204 FD40 SBRC R20,0
0205 9AD8 SBI 0x1B,0
(0093) if (wordout & 0x0002) PORT_ATA_DATA1_OUT |= 0x04;
0206 FD41 SBRC R20,1
0207 9ADA SBI 0x1B,2
(0094) if (wordout & 0x0004) PORT_ATA_DATA1_OUT |= 0x10;
0208 FD42 SBRC R20,2
0209 9ADC SBI 0x1B,4
(0095) if (wordout & 0x0008) PORT_ATA_DATA1_OUT |= 0x40;
020A FD43 SBRC R20,3
020B 9ADE SBI 0x1B,6
(0096) if (wordout & 0x0010) PORT_ATA_DATA2_OUT |= 0x80;
020C FD44 SBRC R20,4
020D 9AAF SBI 0x15,7
(0097) if (wordout & 0x0020) PORT_ATA_DATA2_OUT |= 0x20;
020E FD45 SBRC R20,5
020F 9AAD SBI 0x15,5
(0098) if (wordout & 0x0040) PORT_ATA_DATA2_OUT |= 0x08;
0210 FD46 SBRC R20,6
0211 9AAB SBI 0x15,3
(0099) if (wordout & 0x0080) PORT_ATA_DATA2_OUT |= 0x02;
0212 FD47 SBRC R20,7
0213 9AA9 SBI 0x15,1
(0100) if (wordout & 0x0100) PORT_ATA_DATA2_OUT |= 0x01;
0214 FD50 SBRC R21,0
0215 9AA8 SBI 0x15,0
(0101) if (wordout & 0x0200) PORT_ATA_DATA2_OUT |= 0x04;
0216 FD51 SBRC R21,1
0217 9AAA SBI 0x15,2
(0102) if (wordout & 0x0400) PORT_ATA_DATA2_OUT |= 0x10;
0218 FD52 SBRC R21,2
0219 9AAC SBI 0x15,4
(0103) if (wordout & 0x0800) PORT_ATA_DATA2_OUT |= 0x40;
021A FD53 SBRC R21,3
021B 9AAE SBI 0x15,6
(0104) if (wordout & 0x1000) PORT_ATA_DATA1_OUT |= 0x80;
021C FD54 SBRC R21,4
021D 9ADF SBI 0x1B,7
(0105) if (wordout & 0x2000) PORT_ATA_DATA1_OUT |= 0x20;
021E FD55 SBRC R21,5
021F 9ADD SBI 0x1B,5
(0106) if (wordout & 0x4000) PORT_ATA_DATA1_OUT |= 0x08;
0220 FD56 SBRC R21,6
0221 9ADB SBI 0x1B,3
(0107) if (wordout & 0x8000) PORT_ATA_DATA1_OUT |= 0x02;
0222 FD57 SBRC R21,7
0223 9AD9 SBI 0x1B,1
(0108)
(0109) ata_write_pulse;
0224 91800062 LDS R24,0x62
0226 778F ANDI R24,0x7F
0227 93800062 STS 0x62,R24
0229 E001 LDI R16,1
022A E010 LDI R17,0
022B 940E0804 CALL _delay_us
022D 91800062 LDS R24,0x62
022F 6880 ORI R24,0x80
0230 93800062 STS 0x62,R24
(0110)
(0111) ata_databus_in;
0232 2422 CLR R2
0233 BA2A OUT 0x1A,R2
0234 BA24 OUT 0x14,R2
0235 940E15C5 CALL pop_gset2
0237 9508 RET
_ata_write_byte:
byteout --> R22
reg --> R20
0238 940E15D7 CALL push_gset2
023A 2F62 MOV R22,R18
023B 2F40 MOV R20,R16
(0112) }
(0113)
(0114) //******************************************************************
(0115) //* WRITE BYTE TO ATA DEVICE
(0116) //*
(0117) //*
(0118) //******************************************************************
(0119) void ata_write_byte(unsigned char reg,unsigned char byteout)
(0120) {
(0121) ata_write_word(reg,(unsigned int)byteout);
023C 2F26 MOV R18,R22
023D 2733 CLR R19
023E 2F04 MOV R16,R20
023F DFB7 RCALL _ata_write_word
0240 940E15C5 CALL pop_gset2
0242 9508 RET
_ata_read_word:
wordin --> R20
reg --> R22
0243 940E15D7 CALL push_gset2
0245 2F60 MOV R22,R16
(0122) }
(0123)
(0124) //******************************************************************
(0125) //* READ WORD FROM ATA DEVICE
(0126) //*
(0127) //*
(0128) //* Mapping : D0-PA0,D1-PA2,D2-PA4,D3-PA6,D4-PC7,D5-PC5,D7-PC3,D7-PC1
(0129) //* D8-PC0,D9-PC2,D10-PC4,D11-PC6,D12-PA7,D13-PA5,D14-PA3,D15-PA1
(0130) //******************************************************************
(0131) unsigned int ata_read_word(unsigned char reg)
(0132) {
(0133) unsigned int wordin = 0;
0246 2744 CLR R20
0247 2755 CLR R21
(0134)
(0135) WDR();
0248 95A8 WDR
(0136) PORT_ATA_IO_CNTL = reg;
0249 93600062 STS 0x62,R22
(0137)
(0138) ata_databus_in;
024B 2422 CLR R2
024C BA2A OUT 0x1A,R2
024D BA24 OUT 0x14,R2
(0139)
(0140) PORT_ATA_IO_CNTL &= ~ATA_IOR;
024E 91800062 LDS R24,0x62
0250 7B8F ANDI R24,0xBF
0251 93800062 STS 0x62,R24
(0141) delay_us(1);
0253 E001 LDI R16,1
0254 E010 LDI R17,0
0255 940E0804 CALL _delay_us
(0142)
(0143) if (PORT_ATA_DATA1_IN & 0x01) wordin |= 0x0001;
0257 9BC8 SBIS 0x19,0
0258 C001 RJMP 0x025A
0259 6041 ORI R20,1
(0144) if (PORT_ATA_DATA1_IN & 0x02) wordin |= 0x8000;
025A 9BC9 SBIS 0x19,1
025B C001 RJMP 0x025D
025C 6850 ORI R21,0x80
(0145) if (PORT_ATA_DATA1_IN & 0x04) wordin |= 0x0002;
025D 9BCA SBIS 0x19,2
025E C001 RJMP 0x0260
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