M8C_SetBank0
    M8C_ClearWDTAndSleep            ; Reset the watch dog

ENDIF ;(SELECT_32K & WAIT_FOR_32K)

    ;-------------------------------------------------------------------------
    ; Crystal is now fully operational (assuming WAIT_FOR_32K was left 
    ; enabled). Now start up PLL lock mode if selected.
    ;-------------------------------------------------------------------------
IF (PLL_MODE)
    M8C_SetBank1
    mov  reg[OSC_CR0],(SELECT_32K_JUST | PLL_MODE_JUST | OSC_CR0_SLEEP_64Hz | OSC_CR0_CPU_3MHz)
    M8C_SetBank0
    M8C_ClearWDTAndSleep            ; Reset the sleep timer

    mov  reg[INT_VC],0              ; Clear all pending interrupts
.WaitFor16ms:
    tst  reg[INT_CLR0],INT_MSK0_SLEEP   ; test the Interrupt Status
    jz  .WaitFor16ms                ; TimeOut occurs on Sleep Timer 16ms
IF  (WAIT_FOR_32K)
ELSE ;!(WAIT_FOR_32K)
    ERROR_PSoC Disabling WAIT_FOR_32K requires that the PLL_Lock must be enabled in user code.
ENDIF ;(WAIT_FOR_32K)
ENDIF ;(PLL_MODE)

    ;-------------------------------------------------------------------------
    ; Set CT block RTopMux to OUT and RBotMux to AGND.  This closes leakage 
    ; paths through the CT blocks.
    ;-------------------------------------------------------------------------
    mov  reg[ACB00CR0],05h
    mov  reg[ACB01CR0],05h
    mov  reg[ACB02CR0],05h
    mov  reg[ACB03CR0],05h

    ;-------------------------------------------------------------------------
    ; All the user selections and UserModule selections are now loaded,
    ; except CPU frequency (CPU is runing at 12 MHz).  Load the PSoC 
    ; configuration with a 12 MHz CPU clock to keep config time short.
    ;-------------------------------------------------------------------------
    lcall LoadConfigInit           ; Configure PSoC blocks per Dev Editor


IF (C_LANGUAGE_SUPPORT)
    call InitCRunTime              ; Initialize for C language
ENDIF ;(C_LANGUAGE_SUPPORT)

    
IF (SUPPLY_VOLTAGE)
    ;-------------------------------------------------------------------------
    ; Nominal 5.0 V operating voltage is selected.
    ; Set the Precision Power-On Reset (PPOR) level for the operating voltage
    ; range selected. In addition, if the SMP is running make sure time was 
    ; given to let Vdd slew up to the set voltage before enabling the reset.
    ;-------------------------------------------------------------------------

IF (SWITCH_MODE_PUMP ^ 1)
    ;-------------------------------------------------------------------------
    ; If using the SMP at 5V, must wait for Vdd to slew from 3.1V to 5V
    ; The sleep interrupt will be used for timing Xtal and PLL startup.
    ;-------------------------------------------------------------------------
    or   reg[INT_MSK0],INT_MSK0_SLEEP   

    M8C_SetBank1
    and  reg[OSC_CR0],~OSC_CR0_SLEEP
    or   reg[OSC_CR0],OSC_CR0_SLEEP_512Hz
    M8C_SetBank0

    M8C_ClearWDTAndSleep         ; Reset the sleep timer

    mov  reg[INT_VC],0           ; Clear all pending interrupts
.WaitFor2ms:
    tst  reg[INT_CLR0],INT_MSK0_SLEEP   ; test the Interrupt Status
    jz  .WaitFor2ms              ; TimeOut occurs on Sleep Timer 2ms
ENDIF ;(SWITCH_MODE_PUMP ^ 1)

IF (CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz) ; Clock is not 24MHz
    ;-------------------------------------------------------------------------
    ; <24 MHz operation is requested, so set PPOR to 3.0V.  If a PPOR level
    ;  of 4.5V is desired, then VLT_CR can be set in user code.
    ;-------------------------------------------------------------------------
    M8C_SetBank1
    and  reg[VLT_CR],~VLT_CR_PORLEV
    or   reg[VLT_CR],VLT_CR_3V0_POR
    M8C_SetBank0

ELSE ;!(CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz)
    ;-------------------------------------------------------------------------
    ; 24 MHz operation, so Vdd >= 4.75V required.
    ;-------------------------------------------------------------------------
    M8C_SetBank1
    and  reg[VLT_CR],~VLT_CR_PORLEV
    or   reg[VLT_CR],VLT_CR_4V75_POR
    M8C_SetBank0
ENDIF ;(CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz)

ELSE ;!(SUPPLY_VOLTAGE)
    ;-------------------------------------------------------------------------
    ; Nominal 3.3 V operating voltage is selected, set the PPOR to 3.0V.
    ;-------------------------------------------------------------------------
    M8C_SetBank1
    and  reg[VLT_CR],~VLT_CR_PORLEV
//  or   reg[VLT_CR],VLT_CR_3V0_POR   ; not needed, 0b00 is 3.0V
    M8C_SetBank0

ENDIF ;(SUPPLY_VOLTAGE)

    ;-------------------------------------------------------------------------
    ; Disable the Sleep interrupt that was used for timing above.  In fact,
    ; no interrupts should be enabled now, so may as well clear the register.
    ;-------------------------------------------------------------------------
    mov  reg[INT_MSK0],0

    ;-------------------------------------------------------------------------
    ; Everything has started OK. Now select requested CPU & sleep frequency.
    ;-------------------------------------------------------------------------
    M8C_SetBank1
    mov  reg[OSC_CR0],(SELECT_32K_JUST | PLL_MODE_JUST | SLEEP_TIMER_JUST | CPU_CLOCK_JUST)
    M8C_SetBank0

    ;-------------------------------------------------------------------------
    ; Global Interrupt are NOT enabled, this should be done in main().
    ; LVD is set but will not occur unless Global Interrupts are enabled. 
    ; Global Interrupts should be as soon as possible in main().
    ;-------------------------------------------------------------------------
    mov  reg[INT_VC],0              ; Clear any pending interrupts which may
                                    ; have been set during the boot process. 
    lcall _main                     ; Call main

__Exit:
    jmp  __Exit                     ; Wait here till power is turned off



;-----------------------------------------------------------------------------
; C Runtime Environment Initialization
; The following code is conditionally assembled.
;-----------------------------------------------------------------------------

IF (C_LANGUAGE_SUPPORT)

InitCRunTime:
    ;-----------------------------
    ; clear bss segment
    ;-----------------------------
    mov  A,0
    mov  [__r0],<__bss_start
BssLoop:
    cmp  [__r0],<__bss_end
    jz   BssDone
    mvi  [__r0],A
    jmp  BssLoop
BssDone:
    ;----------------------------
    ; copy idata to data segment
    ;----------------------------
    mov  A,>__idata_start
    mov  X,<__idata_start
    mov  [__r0],<__data_start
IDataLoop:
    cmp  [__r0],<__data_end
    jz   IDataDone
    push A
    romx
    mvi  [__r0],A
    pop  A
    inc  X
    adc  A,0
    jmp  IDataLoop
IDataDone:
    ret

ENDIF ;(C_LANGUAGE_SUPPORT)


;-----------------------------------------------------------------------------
; RAM segments for C CONST, static & global items
;-----------------------------------------------------------------------------
    AREA lit
__lit_start:

    AREA idata
__idata_start:

    AREA func_lit
__func_lit_start:

    AREA psoc_config(ROM,REL,CON)
__psoc_config_start:

    AREA UserModules(ROM,REL,CON)
__usermodules_start:
;---------------------------------------------
;         CODE segment for general use
;---------------------------------------------
    AREA text(ROM,REL,CON)
__text_start:

;---------------------------------------------
;         Begin RAM area usage
;---------------------------------------------
    AREA data(RAM,REL,CON)
__data_start:

    AREA virtual_registers(RAM,REL,CON)
__virtual_registers_end:

;---------------------------------------------
;         RAM segment for general use
;---------------------------------------------
    AREA bss(RAM,REL,CON)
__bss_start:

;end of file