# Setup script for the Atmel AT91 board
# This is only required if the Angel ROM monitor does not do the board setup

# first, tell the wiggler/raven to use a slow clock for JTAG
delay slow

#Disable External Watchdog assertion
memwrite long 0xffff8008 0x0

# At reset, the main clock is the output of the Slow clock oscillator, i.e 32,768KHz
# Set up the Clock frequency to run at 32,768 Mhz with PLLB / PLLCOUNT = 197 (6ms, 0xC5), MUL=999(0x3E7), PLLB
memwrite long 0xffff4020 0xC503E708

# Wait for PMC_PLL_LOCK Bit in the PMC_SR equals 1.
sleep 1

# Commuting from Slow Clock (32,768Khz) to PLLB @32,768Mhz / PLLCOUNT = 197 (6ms, 0xC5), MUL=999(0x3E7), CSS= PLL, PLLB
memwrite long 0xffff4020 0x2003E798

# Wait for the PLL is stabilized
sleep 1

# tell the wiggler/raven to resume using a fast clock
delay fast

# --------------------------------------------------------
# Now the Master clock is the output of PLLB @ 32,768MHz -
# --------------------------------------------------------


# EBI_CSR0 connected to the flash memory.
# Settings : EBI_BA=0x01000000 / EBI_CSEN / EBI_BAT_BYTE_WRITE / EBI_TDF_2 / EBI_PAGES_16M / EBI_NWS_3 / EBI_DBW_16
memwrite long 0xffe00000 0x01002529

# EBI_CSR1 connected to the External SRAM memory.
# Settings : EBI_BA=0x02000000 / EBI_CSEN / EBI_BAT_BYTE_WRITE / EBI_TDF_0 / EBI_PAGES_16M / EBI_NWS_1 / EBI_DBW_16
memwrite long 0xffe00004 0x02002121

# REMAP Done
memwrite long 0xffe00020 0x00000001

#2M bytes per CS
memwrite long 0xffe00024 0x00000006