//******************************************************************
//                                                                
// ATA.H - ATA register definitions and ATA global structure 
// definition.
//
//*****************************************************************

//
// ATA Command Registers
//
#define DATAREGISTER         0x00
#define ERRORREGISTER        0x01
#define FEATURESREGISTER     0x01
#define SECTORCOUNTREGISTER  0x02
#define SECTORNUMBERREGISTER 0x03
#define CYLINDERLOWREGISTER  0x04
#define CYLINDERHIGHREGISTER 0x05
#define DEVICEHEADREGISTER   0x06
#define COMMANDREGISTER      0x07
#define STATUSREGISTER       0x07

//
// ATA Control Registers
//
#define DEVICECONTROLREGISTER   0x06
#define ALTERNATESTATUSREGISTER 0x06


//
// ATA Register Bit Masks
//
#define ATASRST  	0x04
#define ATAnIEN  	0x02
#define ATADEV   	0x10
#define ATAABRT  	0x04
#define ATABSY   	0x80
#define ATADRDY  	0x40
#define ATADRQ   	0x08
#define ATAERR   	0x01
#define ATADEVFAULT	0x20
#define ATAWRITEFAULT	0x20
#define ATASERVICE 	0x10
#define ATACORRECTED	0x04
#define ATAINDEX	0x02


//
// bits 7-4 of the device/head reg
//
#define DEVICEHEAD_DEV0 0x00    // select device 0
#define DEVICEHEAD_DEV1 0x10    // select device 1

//
// ATAPI Interrupt Reason bits in the Sector Count reg (CB_SC)
//

#define CB_SC_P_TAG    0xf8   // ATAPI tag (mask)
#define CB_SC_P_REL    0x04   // ATAPI release
#define CB_SC_P_IO     0x02   // ATAPI I/O
#define CB_SC_P_CD     0x01   // ATAPI C/D

//
// bits 7-4 of the device/head (CB_DH) reg
//
#define CB_DH_DEV0 0x00    // select device 0   **was a0
#define CB_DH_DEV1 0x10    // select device 1   **was b0

//
// digital output reg (CB_DC) bits
//
#define CB_DC_HD15   0x08  // bit should always be set to one
#define CB_DC_SRST   0x04  // soft reset
#define CB_DC_NIEN   0x02  // disable interrupts

//
// ATA command and control addresss
//
#define ATACommandBaseAddress			0x50000000
#define ATAControlBaseAddress			0x50000008

#define CMD_PACKET   				0xA0

//
// ATA register command information structure
//
typedef struct
{
   unsigned char cmd;         // command code
   unsigned char fr1;         // feature reg before
   unsigned char sc1;         // sec cnt before
   unsigned char sn1;         // sec num before
   unsigned char cl1;         // cyl low before
   unsigned char ch1;         // cyl high before
   unsigned char dh1;         // device head before
   unsigned char dc1;         // device control before
   unsigned char ec;          // detailed error code
   unsigned char to;          // not zero if time out error
   unsigned char st2;         // status reg after
   unsigned char as2;         // alt status reg after
   unsigned char er2;         // error reg after
   unsigned char sc2;         // sec cnt after
   unsigned char sn2;         // sec num after
   unsigned char cl2;         // cyl low after
   unsigned char ch2;         // cyl high after
   unsigned char dh2;         // device head after
   long totalBytesXfer;       // total bytes transfered
   unsigned int failbits;     // failure bits (ATAPI protocol errors)
      #define FAILBIT15 0x8000   // extra interrupts detected
      #define FAILBIT14 0x4000
      #define FAILBIT13 0x2000
      #define FAILBIT12 0x1000
      #define FAILBIT11 0x0800
      #define FAILBIT10 0x0400
      #define FAILBIT9  0x0200
      #define FAILBIT8  0x0100   // SC( CD/IO bits) wrong at end of cmd
      #define FAILBIT7  0x0080   // byte count odd at data packet xfer time
      #define FAILBIT6  0x0040   // byte count wrong at data packet xfer time
      #define FAILBIT5  0x0020   // SC (IO bit) wrong at data packet xfer time
      #define FAILBIT4  0x0010   // SC (CD bit) wrong at data packet xfer time
      #define FAILBIT3  0x0008   // byte count wrong at cmd packet xfer time
      #define FAILBIT2  0x0004   // SC wrong at cmd packet xfer time
      #define FAILBIT1  0x0002   // got interrupt before cmd packet xfer
      #define FAILBIT0  0x0001   // slow setting BSY=1 or DRQ=1 after AO cmd
   long drqPackets;           // number of PIO DRQ packets
} REGCMDINFO;