;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 
 ; $Workfile:   bootloader_arm.s  $ 
 ; $Revision:   0.00  $ 
 ; $Author:     AnvikE  $ 
 ; $Date:       Mar 06 2003   $ 
 ; 
 ; Project:     LH754XX
 ; 
 ; Description: 
 ;  This file implements boot code for the KEV754XX chip.
 ; 
 ; Revision History: 
 ; 				
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;  
 ; 
 ;  Copyright (c) 2002 Sharp Microelectronics of the Americas 
 ; 
 ;  All rights reserved 
 ; 
 ;  SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION 
 ;  OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE, 
 ;  AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 ;  SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE. 
 ; 
 ;  SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
 ;  FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 ;  SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE 
 ;  FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS. 
 ; 				
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
	
	AREA    BootInit, CODE, READONLY
	CODE32
	INCLUDE bootloader_arm.i
	IMPORT |Image$$RO$$Base|
	IMPORT |Image$$RO$$Limit|
	EXPORT __start		; export entry point to the linker
	; The code starts here 
__start
	; This is the location of the required interrupt
	; vectors that are used by the arm core to handle
	; system faults.
	;		
	B   resetHandler	; run out of the ROM Physical location   ;
	B   undefHandler	; 0x04 - undefined instruction           
	B   swiHandler		; 0x08 - software interrupt              
	B   prefetchHandler	; 0x0C - prefetch abort                  
	B   abortHandler	; 0x10 - data abort                      
	NOP                     ; reserved vector                        
        LDR pc, [pc, #-0xFF0]   ; 0x18 instruction to invoke VIC for IRQ 
fiqHandler	
undefHandler
swiHandler
prefetchHandler
abortHandler
	; All exceptions are handled by a default handler for now. The user
	; or operating system can add functionality at run time if they wish.
	; Note: To install handlers at a later time requires that the system 
	; have volatile memory mapped to 0. This can be accomplished via the 
	; remap register.
	 
	B   faultHandler

resetHandler	
	; This section set up the system clocks to 50Mhz for the default
	 
	MOV	r0, #RCPC_SYSCLK_PRESCALE_DEFAULT
	LDR	r1, =RCPC_REG_BASE
	STR	r0, [r1,#RCPC_SYSCLK_PRESCALE_OFFSET]

	; This section inits all of the stacks for the different modes
	; that the arm core can run in (IRQ, SVC mode etc ...)
	; Note: All of individual mode stacks point to the same location
	; in TCM memory. This was done for simplicity since there is no
	; exception handler installed, this can be done by the user or an
	; operating system at run time. The fault handler basically sets up
	; the timer and goes back to blinking the led in the at the idle
	; loop. If the user breaks in with debugger after an exception they
	; can look at the lrm and sp to determine which execption took place,
	; and where the stack pointer was when the fault happened.
	 
modeInit
	; All interrupts disabled at core 	
	MOV	r1, #I_MASK
	ADD     r1, r1, #F_MASK	

	; Enter IRQ mode and setup the IRQ stack pointer 
	ORR	r0, r1, #MODE_IRQ	
	MSR	cpsr_cxsf, r0
	LDR	r13, =EXCEPTION_STACK
	
	; Enter FIQ mode and setup the FIQ stack pointer 
	ORR	r0, r1, #MODE_FIQ 	
 	MSR	cpsr_cxsf, r0
	LDR	r13, =EXCEPTION_STACK
	
	; Enter Abort mode and setup the Abort stack pointer 
	ORR	r0, r1, #MODE_ABORT	
	MSR	cpsr_cxsf, r0
	LDR	r13, =EXCEPTION_STACK
	
	; Enter Undefined mode and setup the Undefined stack pointer 
	ORR	r0, r1, #MODE_UNDEF	
	MSR	cpsr_cxsf, r0
	LDR	r13, =EXCEPTION_STACK

	; Enter System mode and setup the User/System stack pointer 
	ORR	r0, r1, #MODE_SYSTEM	
	MSR	cpsr_cxsf, r0
	LDR	r13, =EXCEPTION_STACK

	; Enter SVC mode and setup the SVC stack pointer 
	ORR	r0, r1, #MODE_SVC		
	MSR	cpsr_cxsf, r0
	LDR	r13,=EXCEPTION_STACK

	; We are now running in service mode and it is time to set up 
	; external memory and chip selects
	 
memoryInit
	; Set up the external bus interface  
	LDR	r0, =EBI_MUX_BASE		; base address of ebi			
	LDR	r1, =EBI_PIN_CONFIG		; config for 3 CS's etc 		
	STR	r1, [r0, #0]			; mem[0xFFFE5000] <- data[0x00005B3F]  

	; Set up chip selects 
	LDR	r0, =SMC_REG_BASE		; base address of SMC		       

	; Setup Flash BCR0 on CS0 
	LDR	r1, =SMC_BCR0_INIT		; register setting for Flash          
	STR	r1, [r0, #SMC_BCR0_OFFSET]	; mem[0xFFFF1000] <- data[0x1C001481] 

	; Setup SRAM BCR1 on CS1 
	LDR	r1, =SMC_BCR1_INIT		; register setting for Sram           
	STR	r1, [r0, #SMC_BCR1_OFFSET]	; mem[0xFFFF1004] <- data[0x10000000] 

	; Setup AHB periferals BCR2 on CS2 
	LDR	r1, =SMC_BCR2_INIT		; register settings                   
	STR	r1, [r0, #SMC_BCR2_OFFSET]	; mem[0xFFFF1008] <- data[0x10000C21] 

bootcodeCopy	
	; Now that the memory controller is set up we want to make a copy
	; of this boot code in internal ram. We are doing this so we can
	; use the remap register to remap flash to 0x60000000, and internal
	; sram to 0. This allows the c applications to install interrupt
	; vectors at 0. So after we remap the memory space we better have
	; a shadow copy of this boot code at 0 or we are going to go off
	; into the weeds.
	LDR	r0, =|Image$$RO$$Base|
	LDR	r1, =INTERNAL_SRAM_BASE		; destination 
	LDR	r2, =|Image$$RO$$Limit|		; end
codeCopy	
	LDR	r3, [r0]			; move the opcode from rom           
	STR	r3, [r1]			; move the opcode to internal memory 
	CMP	r0, r2           
	BEQ	switchCheck			; are we done the copy yet	      
	ADD	r0, r0, #4			; increment source pointer           
	ADD	r1, r1, #4		        ; increment destination pointer      
	B	codeCopy

switchCheck
	; Now we are going to check the switch on the user board to determone
	; if we are going to execute a user application or go to the idle loop
	; where we sit a blink the green led.
	; Switch Mappings:
	; 1 - ON - copy code from sector 0x02 to 0x44000000
	; 2 - ON - copy code from sector 0x01 to 0x44000000
	 
	LDR	r0, =DIP_SWITCH_ADRS	; set up the switch base address 
	LDRB	r1, [r0, #0]		; get the switch current setting 

	; Run the Angel application 
	MOV	r2, #ANGEL_DEMO
	LDR	r0, =ANGEL_APP_BASE
	LDR	r3, =ANGEL_APP_SIZE
	MOV	r4, #0x01	
	LDR	r5,	=ANGEL_ENTRY
	CMP	r1, r2
	BEQ	appLoadInit

	; Run the User demo application 
	MOV	r2, #USER_DEMO
	LDR	r0, =USER_APP_BASE
	LDR	r3, =USER_APP_SIZE
	MOV	r4, #0x01	
	LDR	r5,	=USER_ENTRY
	CMP	 r1, r2
	BEQ	appLoadInit
	MOV	r4, #0
	B	memoryRemap	
	
appLoadInit
	MOV	r1, r5			; destination in Sram           
	MOV	r2, r3			; Max number of bytes per demo  
	ADD	r2, r2, r0              ; The end address of the demo   

appLoad
	LDR	r3, [r0]		; move the opcode from rom           
	STR	r3, [r1]		; move the opcode to external memory 
	CMP	r0, r2           
	BEQ	memoryRemap		; are we done the copy yet	      
	ADD	r0, r0, #4		; increment source pointer           
	ADD	r1, r1, #4		; increment destination pointer      
	B	appLoad
	
memoryRemap	
	; We are now remapping the memory chip selects so that it will look
	; like the memory for flash has been mapped to 0x04000000 and internal
	; sram is mapped to 0.
	 
	LDR	r0, =RCPC_REG_BASE	
	MOV	r1, #RCPC_REMAP_INTERNAL_RAM
	STR	r1, [r0, #RCPC_REMAP_OFFSET] ; mem[0xFFFF1008] <- data[0x00000002] 
			
	; Now lets set up the c stack and put the current mode stack 
	; (service mode) at the top of external SRAM. The c startup code should 
	; take care of this but ya never know, and besides it won't hurt.
	 
	LDR	r13,=C_STACK

demoExecute	
	; Now that we are ready to go to the idle loop, lets see if the
	; user dip switch has been set to user demo mode.
	; Note: The switch state of 1 means that we should execute from
	; 0x44000000. This value was saved in r4
	 
	MOV	r0, #1
	CMP	r0, r4
	BNE	idleLoopStart
	MOV	pc, r5 

idleLoopStart	
	; The rest of the code sets up a timer compare register and spins on
	; the counter until it gets a compare match. Once the compare match is
	; determined the green led on the board is toggled between the on/off
	; state.
	 
timerInit		
	; set up Port D Bit 1 as an output 
	MOV	r0, #GPIO_D1			; keep the GPIO base address in r3 
	LDR	r3, =GPIO_REG_BASE		
	STR	r0, [r3,#GPIO_PDDDR_OFFSET]

	; Configure Timer 0 to be clocked as slowly as possible 
	LDR	r1, =TIMER0_REG_BASE		; keep the base address of TIMER0 in r1  
	MOV	r0, #TIMER0_CTRL_INIT	
	STR	r0, [r1, #TIMER0_CTRL_REG_OFFSET]
	MOV	r2,#TIMER0_STATUS_CMP1    

ledToggle	
        LDR     r0,[r3,#GPIO_PDDR_OFFSET]
        EOR     r0,r0,#GPIO_D1
	STR     r0,[r3,#GPIO_PDDR_OFFSET]

	; wait for TIMER0 compare match 
idleLoop	
	LDR     r0,[r1,#TIMER0_STATUS_REG_OFFSET]
	TST     r0,r2
	beq     idleLoop		

	; At compare match clear the count 
	LDR     r0,[r1,#TIMER0_CTRL_REG_OFFSET]
	ORR     r0,r0,#TIMER0_CTRL_COUNT_CLEAR
	STR     r0,[r1,#TIMER0_CTRL_REG_OFFSET]

	; now that there is no compare match, clear the compare match status 
	STR     r2,[r1,#TIMER0_STATUS_REG_OFFSET]
	B	ledToggle

faultHandler	
	B       timerInit           ; spin
	END