.EQU  MODE_BITS,0x1F	@ Bit mask for mode bits in CPSR
.EQU  USR_MODE,	0x10		@ User mode
.EQU  FIQ_MODE,	0x11		@ Fast Interrupt Request mode
.EQU  IRQ_MODE,	0x12		@ Interrupt Request mode
.EQU  SVC_MODE,	0x13		@ Supervisor mode
.EQU  ABT_MODE,	0x17		@ Abort mode
.EQU  UND_MODE,	0x1B		@ Undefined Instruction mode
.EQU  SYS_MODE,	0x1F		@ System mode


.text
reset:  ldr      pc,=cstartup      @  0x0000,0000: RESET Vector
        ldr      pc,=0x0000024     @  0x0000,0004:
        ldr      pc,=0x0000028     @  0x0000,0008:
        ldr      pc,=0x000002c     @  0x0000,000C:
        ldr      pc,=0x0000030     @  0x0000,0010:
        nop                        @  0x0000,0014:
        ldr      pc,[pc,#-0xff0]   @  0x0000,0018: Jump to addr in "VICVectAddr" 0xFFFF0030
        ldr      pc,=0x000003c     @  0x0000,001C: 

@ ---------------------------------------------------------------
@  ?CSTARTUP
@ ---------------------------------------------------------------

@  RTMODEL attributes ensure that
@		RTMODEL "__endian", ENDIAN_MODE
@		RTMODEL "__thumb_aware", "enabled"
@		RTMODEL "__cpu_mode", "*"       @  CPU_MODE_NAME
@		RTMODEL "__code_model", "*"	@  Match all code models

@  Declare segment used with SFE below
@#ifdef _ECPLUSPLUS
@		RSEG	DIFUNCT(2)
@#endif /* _ECPLUSPLUS */

@		RSEG	IRQ_STACK:DATA(2)
@		RSEG	SVC_STACK:DATA:NOROOT(2)
@		RSEG	CSTACK:DATA(2)
@		RSEG	ICODE:CODE:NOROOT(2)
@		PUBLIC	?cstartup
@		EXTERN	__segment_init
@		EXTERN	__low_level_init
@#ifdef _ECPLUSPLUS
@		EXTERN	__call_ctors
@#endif /*  _ECPLUSPLUS */
@		EXTERN	main
@		EXTERN  exit
@		EXTERN	_exit

@  Execution starts here.
@  After a reset, the mode is ARM, Supervisor, interrupts disabled.

		.LTORG

cstartup:

@  Initialize the stack pointers.
@  The pattern below can be used for any of the exception stacks:
@  FIQ, IRQ, SVC, ABT, UND, SYS.
@  The USR mode uses the same stack as SYS. 
@  The stack segments must be defined in the linker command file,
@  and be declared above.
		mrs	r0,cpsr				@  Original PSR value
		bic	r0,r0,#MODE_BITS		@  Clear the mode bits
		orr	r0,r0,#IRQ_MODE			@  Set IRQ mode bits
		msr	cpsr_c,r0			@  Change the mode
		ldr	sp,=0x2030a380 @SFE(IRQ_STACK) & 0xFFFFFFF8	@  End of IRQ_STACK

		bic	r0,r0,#MODE_BITS		@  Clear the mode bits
		orr	r0,r0,#SVC_MODE			@  Set Supervisor mode bits
		msr	cpsr_c,r0		        @  Change the mode
		ldr	sp,=0x2030a180  @SFE(CSTACK) & 0xFFFFFFF8	@  End of CSTACK


/*
 * @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@.
*/

    /*
     * At the end of the reset sequence, MMU, Icache, Dcache,
     * and write buffer are all disabled.
     * Also IRQs and FIQs are disabled in the processor's CPSR
     * The operating mode is SVC (supervisory mode), and the
     * PC is vectored at 0x00000000. A branch in 0x00000000
     * brings us directly here.
     *
     */


	ldr	pc, =coldstart_1
	nop

coldstart_1:
	
    /* Mask off all IRQs and FIQs */
    ldr r2, =0xffffffff	        	/* clear all bits */
    ldr r1, =0xfffff014
    str r2, [r1]

    /*
     * Initialize the LH75401 Clocks
     */
	@ unlock RPC and set HCLK as CLKOUT
        ldr r2, =0x00000263
        ldr r1, =0xfffe2000
    str r2, [r1]

	@ set FCLK to PLL/4 (77.41Mhz)
	ldr r2, =0x00000002
	ldr r1, =0xfffe201c
    str r2, [r1]

	@ set HCLK to PLL/6 (51.61Mhz) - This also sets the SDRAM clock
	@ and the staic memory clock
	ldr r2, =0x00000003
	ldr r1, =0xfffe2018
    str r2, [r1]

	@ enable peripheral clocks
	ldr r2, =0x00000000
	ldr r1, =0xfffe2024
    str r2, [r1]
	ldr r1, =0xfffe2028
    str r2, [r1]

	@ enable sdram clocks
	ldr r2, =0x00000000
	ldr r1, =0xfffe202c
    str r2, [r1]

	@ Peripheral Clock select Register
	ldr r2, =0x00000000
	ldr r1, =0xfffe2030
    str r2, [r1]

	@ enable all memory pins
	ldr r2, =0x000000ef
	ldr r1, =0xfffe5000
    str r2, [r1]

	@ enable all LCD pins
	ldr r2, =0x1fbeda9e
	ldr r1, =0xfffe5004
    str r2, [r1]

	@ enable uart0 and uart1
	ldr r2, =0x00000003
	ldr r1, =0xfffe5010
    str r2, [r1]

        @ disable SSP Multiplex
	ldr r2, =0x00000000
	ldr r1, =0xfffe5014
    str r2, [r1]

	@ enable clkout and nWAIT
	ldr r2, =0x00000402
	ldr r1, =0xfffe5008
    str r2, [r1]

	@ DMA Multiplex
	ldr r2, =0x00000000
	ldr r1, =0xfffe500C
    str r2, [r1]


	@ Setup nCS0 - StrataFLASH, 8Mbytes, 200nsec, 16-btis
	ldr r2, =0x13005540
	ldr r1, =0xffff1000
	str r2, [r1]


	@ Setup nCS1 - CPLD
	ldr r2, =0x1000FFE9
	ldr r1, =0xffff1004
	str r2, [r1]

	@ Setup nCS2 - CS-AD
	ldr r2, =0x1000FFE9
	ldr r1, =0xffff1008
	str r2, [r1]


	/* pause for ~200usec for clocks to stabliz*/
	bl delay_200
	@ ldr pc,=delay_200
	

    /*
     * Initialize SDRAM Controller
     */
	@ Setup SDRAM
	@ issue 2 NOP
        ldr r2, =0x00000003
        ldr r1, =0xffff2004
    str r2, [r1]
	bl	delay_200
	
    str r2, [r1]
	bl	delay_200
	

	@ issue Precharge All
    ldr r2, =0x00000001
    ldr r1, =0xffff2004
    str r2, [r1]
	bl	delay_200
	

	@ set refresh timer to 16 clocks to a force bunch right away
    ldr r2, =0x00000010
    ldr r1, =0xffff2008
    str r2, [r1]
	bl	delay_200
	

	@ now set to the final number to ~15usec @ 51Mhz
    ldr r2, =0x000002e0
    ldr r1, =0xffff2008
    str r2, [r1]
	bl	delay_200
	

	@ set MRS mode
    ldr r2, =0x00000002
    ldr r1, =0xffff2004
    str r2, [r1]
	bl	delay_200
	

	@ 0x22 sets burst mode and cas latency for bank 0
    ldr r1, =0x20022000
    ldr r2, [r1]
	bl	delay_200
	

	@ Write SDRCConfig0, for CAS latency = 2, RAS to CAS = 2, 32-bit, 4 bank
    ldr r2, =0x01A00088
    ldr r1, =0xffff2000
    str r2, [r1]
	bl	delay_200
	

	@ set Normal mode
    ldr r2, =0x00000000
    ldr r1, =0xffff2004
    str r2, [r1]
	bl	delay_200
        ldr  pc,=init_sdram_end
        
init_sdram_end:
	b .
	        
 @ simple delay loop
 delay_200:
	ldr		r3, =200			/* loop count */
 delay_loop:
	subs	        r3,r3,#1
	bne		delay_loop
	nop
        mov		pc, lr

.end