////////////////////////////////////////////////////////////////////////////////// Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.//////////////////////////////////////////////////////////////////////////////////   ____  ____//  /   /\/   /// /___/  \  /    Vendor: Xilinx// \   \   \/     Version: I.24//  \   \         Application: netgen//  /   /         Filename: motor_synthesis.v// /___/   /\     Timestamp: Mon Nov 20 15:12:08 2006// \   \  /  \ //  \___\/\___\//             // Command	: -intstyle ise -w -dir netgen/synthesis -ofmt verilog -sim motor.ngc motor_synthesis.v // Device	: xc2s15-5-vq100// Input file	: motor.ngc// Output file	: F:\practice\PLD\motor\netgen\synthesis\motor_synthesis.v// # of Modules	: 1// Design Name	: motor// Xilinx        : C:\Xilinx//             // Purpose:    //     This verilog netlist is a verification model and uses simulation //     primitives which may not represent the true implementation of the //     device, however the netlist is functionally correct and should not //     be modified. This file cannot be synthesized and should only be used //     with supported simulation tools.//             // Reference:  //     Development System Reference Guide, Chapter 23//     Synthesis and Simulation Design Guide, Chapter 6//             ////////////////////////////////////////////////////////////////////////////////`timescale 1 ns/1 psmodule motor (  clk, dir, reset, A, B, C);  input clk;  input dir;  input reset;  output A;  output B;  output C;  wire clk_BUFGP_3;  wire dir_IBUF_4;  wire reset_IBUF_5;  wire A_OBUF_6;  wire B_OBUF_7;  wire C_OBUF_8;  wire N15;  wire N16;  wire N17;  wire N18;  wire N19;  wire N28;  wire N29;  wire N30;  wire N31;  wire N32;  wire N33;  wire N34;  wire N35;  wire [2 : 0] phase1;  wire [1 : 0] _n0012;  defparam phase1_0.INIT = 1'b1;  FD phase1_0 (    .D(_n0012[0]),    .C(clk_BUFGP_3),    .Q(phase1[0])  );  defparam phase1_1.INIT = 1'b0;  FD phase1_1 (    .D(_n0012[1]),    .C(clk_BUFGP_3),    .Q(phase1[1])  );  BUFGP clk_BUFGP (    .I(clk),    .O(clk_BUFGP_3)  );  IBUF dir_IBUF (    .I(dir),    .O(dir_IBUF_4)  );  IBUF reset_IBUF (    .I(reset),    .O(reset_IBUF_5)  );  OBUF A_OBUF (    .I(A_OBUF_6),    .O(A)  );  OBUF B_OBUF (    .I(B_OBUF_7),    .O(B)  );  OBUF C_OBUF (    .I(C_OBUF_8),    .O(C)  );  FDS A_0 (    .D(N15),    .S(reset_IBUF_5),    .C(clk_BUFGP_3),    .Q(A_OBUF_6)  );  FDR B_1 (    .D(N16),    .R(reset_IBUF_5),    .C(clk_BUFGP_3),    .Q(B_OBUF_7)  );  FDR C_2 (    .D(N17),    .R(reset_IBUF_5),    .C(clk_BUFGP_3),    .Q(C_OBUF_8)  );  defparam phase1_2.INIT = 1'b0;  FDR phase1_2 (    .D(N18),    .R(reset_IBUF_5),    .C(clk_BUFGP_3),    .Q(phase1[2])  );  MUXF5 \_n0012<0>1111  (    .I0(N28),    .I1(N29),    .S(phase1[2]),    .O(_n0012[0])  );  MUXF5 _n00091 (    .I0(N30),    .I1(N31),    .S(phase1[0]),    .O(N15)  );  MUXF5 _n00101 (    .I0(N32),    .I1(N33),    .S(phase1[0]),    .O(N16)  );  MUXF5 _n00111 (    .I0(N34),    .I1(N35),    .S(phase1[0]),    .O(N17)  );  defparam \_n0012<1>1_SW0 .INIT = 4'hD;  LUT2_L \_n0012<1>1_SW0  (    .I0(phase1[2]),    .I1(dir_IBUF_4),    .LO(N19)  );  defparam \_n0012<1>1 .INIT = 16'hFF6A;  LUT4_L \_n0012<1>1  (    .I0(phase1[0]),    .I1(phase1[1]),    .I2(N19),    .I3(reset_IBUF_5),    .LO(_n0012[1])  );  defparam \_n0012<2>21 .INIT = 16'h78CC;  LUT4_L \_n0012<2>21  (    .I0(dir_IBUF_4),    .I1(phase1[2]),    .I2(phase1[0]),    .I3(phase1[1]),    .LO(N18)  );  defparam \_n0012<0>1111_F .INIT = 16'h0504;  LUT4_L \_n0012<0>1111_F  (    .I0(reset_IBUF_5),    .I1(phase1[1]),    .I2(phase1[0]),    .I3(dir_IBUF_4),    .LO(N28)  );  defparam \_n0012<0>1111_G .INIT = 16'h020F;  LUT4_L \_n0012<0>1111_G  (    .I0(phase1[1]),    .I1(dir_IBUF_4),    .I2(reset_IBUF_5),    .I3(phase1[0]),    .LO(N29)  );  defparam _n00091_F.INIT = 16'hFFF4;  LUT4_L _n00091_F (    .I0(phase1[2]),    .I1(A_OBUF_6),    .I2(phase1[1]),    .I3(dir_IBUF_4),    .LO(N30)  );  defparam _n00091_G.INIT = 16'hEBAB;  LUT4_L _n00091_G (    .I0(dir_IBUF_4),    .I1(phase1[2]),    .I2(phase1[1]),    .I3(A_OBUF_6),    .LO(N31)  );  defparam _n00101_F.INIT = 16'h050E;  LUT4_L _n00101_F (    .I0(phase1[1]),    .I1(B_OBUF_7),    .I2(dir_IBUF_4),    .I3(phase1[2]),    .LO(N32)  );  defparam _n00101_G.INIT = 16'h080A;  LUT4_L _n00101_G (    .I0(phase1[1]),    .I1(B_OBUF_7),    .I2(dir_IBUF_4),    .I3(phase1[2]),    .LO(N33)  );  defparam _n00111_F.INIT = 16'h2322;  LUT4_L _n00111_F (    .I0(phase1[2]),    .I1(dir_IBUF_4),    .I2(phase1[1]),    .I3(C_OBUF_8),    .LO(N34)  );  defparam _n00111_G.INIT = 16'h080A;  LUT4_L _n00111_G (    .I0(phase1[2]),    .I1(C_OBUF_8),    .I2(dir_IBUF_4),    .I3(phase1[1]),    .LO(N35)  );endmodule`timescale  1 ps / 1 psmodule glbl ();    parameter ROC_WIDTH = 100000;    parameter TOC_WIDTH = 0;    wire GSR;    wire GTS;    wire PRLD;    reg GSR_int;    reg GTS_int;    reg PRLD_int;//--------   JTAG Globals --------------    wire JTAG_TDO_GLBL;    wire JTAG_TCK_GLBL;    wire JTAG_TDI_GLBL;    wire JTAG_TMS_GLBL;    wire JTAG_TRST_GLBL;    reg JTAG_CAPTURE_GLBL;    reg JTAG_RESET_GLBL;    reg JTAG_SHIFT_GLBL;    reg JTAG_UPDATE_GLBL;    reg JTAG_SEL1_GLBL = 0;    reg JTAG_SEL2_GLBL = 0 ;    reg JTAG_SEL3_GLBL = 0;    reg JTAG_SEL4_GLBL = 0;    reg JTAG_USER_TDO1_GLBL = 1'bz;    reg JTAG_USER_TDO2_GLBL = 1'bz;    reg JTAG_USER_TDO3_GLBL = 1'bz;    reg JTAG_USER_TDO4_GLBL = 1'bz;    assign (weak1, weak0) GSR = GSR_int;    assign (weak1, weak0) GTS = GTS_int;    assign (weak1, weak0) PRLD = PRLD_int;    initial begin	GSR_int = 1'b1;	PRLD_int = 1'b1;	#(ROC_WIDTH)	GSR_int = 1'b0;	PRLD_int = 1'b0;    end    initial begin	GTS_int = 1'b1;	#(TOC_WIDTH)	GTS_int = 1'b0;    endendmodule