;==================================================================================
; The information contained herein is the exclusive property of
; Sunplus Technology Co. And shall not be distributed, reproduced,
; or disclosed in whole in part without prior written permission.
;       (C) COPYRIGHT 2004   SUNPLUS TECHNOLOGY CO.                                  
;                   ALL RIGHTS RESERVED
; The entire notice above must be reproduced on all authorized copies.
;==================================================================================
										
;==================================================================================
;	Project Name	:	
;	Applied Body	:	SPMC65P2404A
;	Firmware version:
;	Programer		:
;	Date			:	2004-8-23
;	Description		:	The program presents an example that delay ( A*2669 ) or 
;                       ( A*2654473)cycles , under default system clock(2654208Hz),
;						they are (A)ms or (A)s.
;						
;	Hardware Connect:	
;	Link File		:	
;	IDE Version		: 	V1.6.5	
;	BODY Version	:	V1.0.0A
;==================================================================================

;************************************************************************************
;*																					*
;*      System Register Define	                                                    *
;*																					*
;************************************************************************************
.INCLUDE		SPMC65P2404A.inc				;Define all hardware,Registers and ports. 
;************************************************************************************

;************************************************************************************
;*																					*
;*      Data memory Define	                                                        *
;*																					*
;************************************************************************************
.PAGE0									;Define values in the range from 00h to FFh
;************************************************************************************
.DATA									;Define data storage section
;************************************************************************************
;*																					*
;*      	 Program Area															*
;*																					*
;************************************************************************************
.CODE
          
.INCLUDE		SoftDelay.asm			;Delay ( A*2669 ) or ( A*2654473)cycles                                                                            
;************************************************************************************
;*																					*
;*      Power on Reset Process	                                                    *
;*																					*
;************************************************************************************
V_Reset:
		sei								;Disable interrupt
		ldx		#C_STACK_BOTTOM			;Initial stack pointer at $00ff
		txs								;Transfer to stack point
			
?L_Main_Loop:							;The example for test

		lda		#5						;Delay 5ms under default system clock(2654208Hz)
		jsr		F_DelayMS
		
		lda		#5						;Delay 5s under default system clock(2654208Hz)
		jsr		F_DelayS
		
		jmp		?L_Main_Loop               

;************************************************************************************
;*																					*
;*      Interrupt service process                         	                        *
;*																					*
;************************************************************************************
V_IRQ:      
		rti           
V_NMI:
		rti
;************************************************************************************
;*																					*
;*      Interrupt Vector Table														*
;*																					*
;************************************************************************************
VECTOR		.SECTION
		DW		V_NMI				;Non-mask interrupt vector(no use)
		DW		V_Reset				;Reset vector
		DW		V_IRQ				;IRQ interrupt vector
;************************************************************************************
;*																					*
;*      End of Interrupt Vector Table												*
;*																					*
;************************************************************************************
.END