;==================================================================================
; The information contained herein is the exclusive property of
; Sunplus Technology Co. And shall not be distributed, reproduced,
; or disclosed in whole in part without prior written permission.
;       (C) COPYRIGHT 2004   SUNPLUS TECHNOLOGY CO.                                  
;                   ALL RIGHTS RESERVED
; The entire notice above must be reproduced on all authorized copies.
;==================================================================================
																					
;==================================================================================
;  Program Name		:	SoftDelay.asm
;  Description		:	The program presents an example that delay ( A*2669 ) or 
;                       ( A*2654473)cycles , under default system clock(2654208Hz),
;						they are (A)ms or (A)s.  		 
;  Reference		:	SPMC65P2404A/2408A Data Sheet
;  Revision history	:
;---------------------------------------------------------------------------------- 
;  Version		Date 		Description
;  1.0.0    	2004-9-11	First Edition
;==================================================================================

.SYNTAX  6502							;process standard 6502 addressing syntax
.LINKLIST								;generate linklist information
.SYMBOLS								;generate symbolic debug information
;************************************************************************************

;**********************************************************************************
.PAGE0				
.DATA				;Define data storage section
;**********************************************************************************
.CODE
;==================================================================================
;	Function:		F_DelayMS
;	Description:	Instruction delay,the length of time is( A*2669 )cycles
;					under the default system clock(2654208Hz),the time of
;					2654 cycles is 1ms.
;	Input:			A
;	Output:			none
;	Destroy:		A,X
;	Stacks:			1
;==================================================================================
;----------------------------------------------------
;		ldx	#dd---------2 cycles
;		dex-------------2 cycles
;		bne	??----------2/3 cycles
;		tax-------------2 cycles
;		txa-------------2 cycles
;		rts-------------6 cycles
;		nop-------------2 cycles
;		default	system clock:2654208Hz
;----------------------------------------------------
F_DelayMS:
		ldy		#10         ;--------------------2 cycles     \ 
?L_Dey:        				;                                 ;
		ldx		#158 		;    2 cycles	     \			  ;
?L_Dex:        				;			         +            ;
		dex					;\789 cycles	     +7959 cycles ;7975 cycles	
		bne		?L_Dex		;/                   +            ;
		   					;					 +            ;  
		dey					;	2 cycles         +            ;  
		bne		?L_Dey		;	2/3 cycles       /            ;
		                                                      ;
		tax					;\                                ;   
		dex					;+--------------------8 cycles    ;    
		txa					;+                        		  ;				
		bne		F_DelayMS	;/            	     			  ;			
?L_Delay_End:												  ;			
		rts					;---------------------6 cycles	  /			
;==================================================================================
;	Function:		F_DelayS
;	Description:	Instruction delay,the length of time is( A*2654473)cycles
;					under the default system clock(2654208Hz),the time of
;					2654208 cycles is 1s.
;	Input:			A
;	Output:			none
;	Destroy:		A,X,Y
;	Stacks:			1
;==================================================================================
;----------------------------------------------------
;		ldx	#dd---------2 cycles
;		dex-------------2 cycles
;		bne	??----------2/3 cycles
;		tax-------------2 cycles
;		txa-------------2 cycles
;		rts-------------6 cycles
;		nop-------------2 cycles
;		default	system clock:2654208Hz
;----------------------------------------------------
F_DelayS:
?L_LOOP:		
		pha						;1 cycles------------------------\										
		ldy		#4				;2 cycles------------------------+					
?L_1S:							;--------------------------------+
		tya						;2 cycles		\		         +    
		pha						;1 cycles	    + 				 +				
		lda		#250			;2 cycles		+				 +		
		jsr		F_DelayMS		;1989756 cycles	+				 +		
		pla						;1 cycles		+ =7959075 cycles+
		tay						;2 cycles		+				 + = 7959090 cycles
		dey						;2 cycles		+				 +
		bne		?L_1S			;2/3 cycles		/				 +
								;								 +
		pla						;1  cycles-----------------------+
		sec 					;1  cycles-----------------------+
		sbc		#1		        ;2  cycles-----------------------+			
		bne		?L_LOOP			;2/3 cycles----------------------+
?L_Delay_End:					;--------------------------------+				
		rts						;6 cycles------------------------/