?? spmc65p2404a.inc
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C_AD_Pin2: EQU %00000100 ; Analog input Port Configuration: channel 2.
C_AD_Pin3: EQU %00001000 ; Analog input Port Configuration: channel 3.
C_AD_Pin4: EQU %00010000 ; Analog input Port Configuration: channel 4.
C_AD_Pin5: EQU %00100000 ; Analog input Port Configuration: channel 5.
C_AD_Pin6: EQU %01000000 ; Analog input Port Configuration: channel 6.
C_AD_Pin7: EQU %10000000 ; Analog input Port Configuration: channel 7.
CB_AD_Pin0: EQU 0 ; Analog input Port Configuration: channel 0 for bit mode.
CB_AD_Pin1: EQU 1 ; Analog input Port Configuration: channel 1 for bit mode.
CB_AD_Pin2: EQU 2 ; Analog input Port Configuration: channel 2 for bit mode.
CB_AD_Pin3: EQU 3 ; Analog input Port Configuration: channel 3 for bit mode.
CB_AD_Pin4: EQU 4 ; Analog input Port Configuration: channel 4 for bit mode.
CB_AD_Pin5: EQU 5 ; Analog input Port Configuration: channel 5 for bit mode.
CB_AD_Pin6: EQU 6 ; Analog input Port Configuration: channel 6 for bit mode.
CB_AD_Pin7: EQU 7 ; Analog input Port Configuration: channel 7 for bit mode.
;
P_AD_Ctrl2: EQU $2A ; A/D converter control 2.
C_AD_CE: EQU %10000000 ; ADC power control bit.(A)
C_AD_Ch0: EQU %00000000 ; 0000:channel 0.
C_AD_Ch1: EQU %00001000 ; 0001:channel 1.
C_AD_Ch2: EQU %00010000 ; 0010:channel 2.
C_AD_Ch3: EQU %00011000 ; 0011:channel 3.
C_AD_Ch4: EQU %00100000 ; 0100:channel 4.
C_AD_Ch5: EQU %00101000 ; 0101:channel 5.
C_AD_Ch6: EQU %00110000 ; 0110:channel 6.
C_AD_Ch7: EQU %00111000 ; 0111:channel 7.
CB_AD_CE: EQU 7 ; ADC power control bit for bit mode.(A)
;
P_AD_DataHi: EQU $2B ; Converted A/D data[9:2] hi.(R)
P_AD_DataLo: EQU $2C ; Converted A/D data[1:0] low.(R)
;
;-----------------------------------------------------------------------------------------------------
P_BUZ_Ctrl: EQU $2D ; Buzzer & Timer base Control.
; Time Base Prescale select bit. (A)
C_TBASE_Dis: EQU %00000000 ; Time Base disable
C_TBASE_Div_128: EQU %00010000 ; Time Base Clk: Fto/2^7.
C_TBASE_Div_256: EQU %00100000 ; Time Base Clk: Fto/2^8.
C_TBASE_Div_512: EQU %00110000 ; Time Base Clk: Fto/2^9.
C_TBASE_Div_1k: EQU %01000000 ; Time Base Clk: Fto/2^10.
C_TBASE_Div_2k: EQU %01010000 ; Time Base Clk: Fto/2^11.
C_TBASE_Div_4k: EQU %01100000 ; Time Base Clk: Fto/2^12.
C_TBASE_Div_8k: EQU %01110000 ; Time Base Clk: Fto/2^13.
; Buzzer frequency select bits.(A)
C_BUZ_Dis: EQU %00000000 ; Buzzer disable
C_BUZ_Div_64: EQU %00000001 ; Buzzer:Fto/2^6.
C_BUZ_Div_128: EQU %00000010 ; Buzzer:Fto/2^7.
C_BUZ_Div_256: EQU %00000011 ; Buzzer:Fto/2^8.
C_BUZ_Div_512: EQU %00000100 ; Buzzer:Fto/2^9.
C_BUZ_Div_1k: EQU %00000101 ; Buzzer:Fto/2^10.
C_BUZ_Div_2k: EQU %00000110 ; Buzzer:Fto/2^11.
C_BUZ_Div_4k: EQU %00000111 ; Buzzer:Fto/2^12.
C_BUZ_Div_8k: EQU %00001000 ; Buzzer:Fto/2^13.
C_BUZ_Div_4: EQU %00001001 ; Buzzer:Fto/2^2.
C_BUZ_Div_8: EQU %00001010 ; Buzzer:Fto/2^3.
C_BUZ_Div_16: EQU %00001011 ; Buzzer:Fto/2^4.
C_BUZ_Div_32: EQU %00001100 ; Buzzer:Fto/2^5.
;
;-----------------------------------------------------------------------------------------------------
; Double Write Register
P_SYS_Ctrl: EQU $30 ; System control.
C_SCR_POR: EQU %10000000 ; Power On Reset Flag.(A)
C_SCR_ERST: EQU %01000000 ; External Reset Flag.(A)
C_SCR_LVR: EQU %00100000 ; Low Voltage Reset Flag.(A)
C_SCR_WDTR: EQU %00001000 ; WDT Reset Flag.(A)
C_SCR_IAR: EQU %00000100 ; Illegal Address Reset Flag.(A)
C_SCR_IIR: EQU %00000001 ; Illegal instruction reset.(A)
CB_SCR_POR: EQU 7 ; Power On Reset Flag for bit mode.(A)
CB_SCR_ERST: EQU 6 ; External Reset Flag for bit mode.(A)
CB_SCR_LVR: EQU 5 ; Low Voltage Reset Flag for bit mode.(A)
CB_SCR_WDTR: EQU 3 ; WDT Reset Flag for bit mode.(A)
CB_SCR_IAR: EQU 2 ; Illegal Address Reset Flag for bit mode.(A)
CB_SCR_IIR: EQU 0 ; Illegal instruction reset for bit mode.(A)
;
P_MODE_Ctrl: EQU $31 ; Operation mode control register.(W)
C_MODE_STOP: EQU $5A ; Enter STOP mode.(W)
C_MODE_HALT: EQU $A5 ; Enter HALT mode.(W)
C_MODE_Reset: EQU $66 ; Reset all of internal modules except CPU.(W)
;
P_WDT_Ctrl: EQU $32 ; Watchdog control register.
C_WDT_SCKEN: EQU %10000000 ; Slow clock enable bit in stop mode.(A)
; Selection bits of watchdog interrupt rate.(A)
C_WDT_RTO: EQU %00000000 ; RTO from Timer0 is selected.
C_WDT_Div_256: EQU %00010000 ; WDI clock = /256.
C_WDT_Div_512: EQU %00100000 ; WDI clock = /512.
C_WDT_Div_1024: EQU %00110000 ; WDI clock = /1024.
C_WDT_Div_2048: EQU %01000000 ; WDI clock = /2048.
C_WDT_Div_4096: EQU %01010000 ; WDI clock = /4096.
C_WDT_Div_8192: EQU %01100000 ; WDI clock = /8192.
C_WDT_Div_16384: EQU %01110000 ; WDI clock = /16384.
CB_WDT_EN: EQU 7 ; Watchdog enable bit in stop mode for bit mode.(A)
;
P_IRQ_Opt1: EQU $34 ; IRQ Option 1 register.
C_IRQOpt1_IRQ3ES: EQU %10000000 ; Polarity control of INT3.(A)
C_IRQOpt1_IRQM3: EQU %01000000 ; INT3 trigger mode selection.(A)
C_IRQOpt1_IRQ2ES: EQU %00100000 ; Polarity control of INT2.(A)
C_IRQOpt1_IRQM2: EQU %00010000 ; INT2 trigger mode selection.(A)
C_IRQOpt1_IRQ1ES: EQU %00001000 ; Polarity control of INT1.(A)
C_IRQOpt1_IRQM1: EQU %00000100 ; INT1 trigger mode selection.(A)
C_IRQOpt1_IRQ0ES: EQU %00000010 ; Polarity control of INT0.(A)
C_IRQOpt1_IRQM0: EQU %00000001 ; INT0 trigger mode selection.(A)
C_IRQOpt1_CAP3ES: EQU %00001000 ; Polarity control of CAP3.(A)
C_IRQOpt1_CAP2ES: EQU %00000010 ; Polarity control of CAP2.(A)
CB_IRQOpt1_IRQ3ES: EQU 7 ; Polarity control of INT3 for bit mode.(A)
CB_IRQOpt1_IRQM3: EQU 6 ; INT3 trigger mode selection for bit mode.(A)
CB_IRQOpt1_IRQ2ES: EQU 5 ; Polarity control of INT2 for bit mode.(A)
CB_IRQOpt1_IRQM2: EQU 4 ; INT2 trigger mode selection for bit mode.(A)
CB_IRQOpt1_IRQ1ES: EQU 3 ; Polarity control of INT1 for bit mode.(A)
CB_IRQOpt1_IRQM1: EQU 2 ; INT1 trigger mode selection for bit mode.(A)
CB_IRQOpt1_IRQ0ES: EQU 1 ; Polarity control of INT0 for bit mode.(A)
CB_IRQOpt1_IRQM0: EQU 0 ; INT0 trigger mode selection for bit mode.(A)
CB_IRQOpt1_CAP3ES: EQU 3 ; Polarity control of CAP3 for bit mode.(A)
CB_IRQOpt1_CAP2ES: EQU 1 ; Polarity control of CAP2 for bit mode.(A)
;
P_IO_Opt: EQU $35 ; I/O slew rate control register.
C_IO_SLOWE: EQU %00000001 ; PB[7:6] slew rate enable selection.(A)
CB_IO_SLOWE: EQU 0 ; PB[7:6] slew rate enable selection for bit mode.(A)
;
P_LVR_Opt: EQU $36 ; LVR Option
C_LVR_V40: EQU %00000001 ; LVR level select bit.(A)
CB_LVR_V40: EQU 0 ; LVR level select bit for bit mode.(A)
;
;-----------------------------------------------------------------------------------------------------
P_SPI_Ctrl0: EQU $38 ; SPI control register 0.
C_SPI_EN: EQU %10000000 ; enable Control bit.
C_SPI_MOD: EQU %01000000 ; operation Mode Master/Slave Mode.
C_SPI_SCKPHA: EQU %00100000 ; clock phase.
C_SPI_SCKPOL: EQU %00010000 ; clock polarity.
C_SPI_SPISMPS: EQU %00001000 ; sample mode selection bit for master mode.
C_SPICS_Div_128: EQU %00000101 ; CPU Clock Selection/128.
C_SPICS_Div_64: EQU %00000100 ; CPU Clock Selection/64.
C_SPICS_Div_32: EQU %00000011 ; CPU Clock Selection/32.
C_SPICS_Div_16: EQU %00000010 ; CPU Clock Selection/16.
C_SPICS_Div_8: EQU %00000001 ; CPU Clock Selection/8.
C_SPICS_Div_4: EQU %00000000 ; CPU Clock Selection/4.
CB_SPI_EN: EQU 7 ; enable Control bit for bit mode.
CB_SPI_MOD: EQU 6 ; operation Mode Master/Slave Mode for bit mode.
CB_SPI_SCKPHA: EQU 5 ; clock phase for bit mode.
CB_SPI_SCKPOL: EQU 4 ; clock polarity for bit mode.
CB_SPI_SPISMPS: EQU 3 ; sample mode selection bit for master mode for bit mode.
;
P_SPI_Ctrl1: EQU $39 ; SPI control register 1.
C_SPI_SMSEN: EQU %10000000 ; SPI Slave Mode Selection enable bit.
C_SPI_SWRST: EQU %01000000 ; software reset bit.
C_SPISPC_Div_4: EQU %00000011 ; sampling clock Div/4.
C_SPISPC_Div_2: EQU %00000010 ; sampling clock Div/2.
C_SPISPC_Div_1: EQU %00000001 ; sampling clock Div/1.
C_SPISPC_Dis: EQU %00000000 ; no sampling.
CB_SPI_SMSEN: EQU 7 ; SPI Slave Mode Selection enable bit for bit mode.
CB_SPI_SWRST: EQU 6 ; software reset bit for bit mode.
;
P_SPI_Status: EQU $3A ; SPI status register
C_SPI_INTIF: EQU %10000000 ; SPI interrupt flag active.
C_SPI_INTEN: EQU %01000000 ; SPI interrupt enable/diable.
C_SPI_TXBF: EQU %00100000 ; transmission buffer full flag.
C_SPI_BUFFull: EQU %00000001 ; buffer full and overwrite.
CB_SPI_INTIF: EQU 7 ; SPI interrupt flag active for bit mode.
CB_SPI_INTEN: EQU 6 ; SPI interrupt enable/diable for bit mode.
CB_SPI_TXBF: EQU 5 ; transmission buffer full flag for bit mode.
CB_SPI_BUFFull: EQU 0 ; buffer full and overwrite for bit mode.
;
P_SPI_TxData: EQU $3B ; SPI Transmit data buffer
P_SPI_RxData: EQU $3C ; SPI Receive data buffer
;
;-----------------------------------------------------------------------------------------------------
P_CAP_Ctrl: EQU $58 ; Capture control
C_CAP_OPT: EQU %10000000 ; Capture option control bit.(A)
C_CAP_IP3: EQU %00100000 ; CAP3 interrupt evoke polarity.
C_CAP_IP2: EQU %00010000 ; CAP2 interrupt evoke polarity.
C_CAP_IP1: EQU %00001000 ; CAP1 interrupt evoke polarity.
C_CAP_IP0: EQU %00000100 ; CAP0 interrupt evoke polarity.
C_CAP1_ES: EQU %00000010 ; Polarity control of capture1 interrupt.
C_CAP0_ES: EQU %00000001 ; Polarity control of capture0 interrupt.
CB_CAP_OPT: EQU 7 ; Capture option control bit for bit mode.(A)
CB_CAP_IP3: EQU 5 ; CAP3 interrupt evoke polarity for bit mode.
CB_CAP_IP2: EQU 4 ; CAP2 interrupt evoke polarity for bit mode.
CB_CAP_IP1: EQU 3 ; CAP1 interrupt evoke polarity for bit mode.
CB_CAP_IP0: EQU 2 ; CAP0 interrupt evoke polarity for bit mode.
CB_CAP1_ES: EQU 1 ; Polarity control of capture1 interrupt for bit mode.
CB_CAP0_ES: EQU 0 ; Polarity control of capture0 interrupt for bit mode.
;
;-----------------------------------------------------------------------------------------------------
P_IOA_Buf: EQU $59
C_IOA_Buf7: EQU %10000000 ; Output data Latch of PORTA bit7.
C_IOA_Buf6: EQU %01000000 ; Output data Latch of PORTA bit6.
C_IOA_Buf5: EQU %00100000 ; Output data Latch of PORTA bit5.
C_IOA_Buf4: EQU %00010000 ; Output data Latch of PORTA bit4.
C_IOA_Buf3: EQU %00001000 ; Output data Latch of PORTA bit3.
C_IOA_Buf2: EQU %00000100 ; Output data Latch of PORTA bit2.
C_IOA_Buf1: EQU %00000010 ; Output data Latch of PORTA bit1.
C_IOA_Buf0: EQU %00000001 ; Output data Latch of PORTA bit0.
P_IOB_Buf: EQU $5A
C_IOB_Buf7: EQU %10000000 ; Output data Latch of PORTB bit7.
C_IOB_Buf6: EQU %01000000 ; Output data Latch of PORTB bit6.
C_IOB_Buf5: EQU %00100000 ; Output data Latch of PORTB bit5.
C_IOB_Buf4: EQU %00010000 ; Output data Latch of PORTB bit4.
C_IOB_Buf3: EQU %00001000 ; Output data Latch of PORTB bit3.
C_IOB_Buf2: EQU %00000100 ; Output data Latch of PORTB bit2.
C_IOB_Buf1: EQU %00000010 ; Output data Latch of PORTB bit1.
C_IOB_Buf0: EQU %00000001 ; Output data Latch of PORTB bit0.
P_IOC_Buf: EQU $5B
C_IOC_Buf3: EQU %00001000 ; Output data Latch of PORTC bit3.
C_IOC_Buf2: EQU %00000100 ; Output data Latch of PORTC bit2.
C_IOC_Buf1: EQU %00000010 ; Output data Latch of PORTC bit1.
C_IOC_Buf0: EQU %00000001 ; Output data Latch of PORTC bit0.
P_IOD_Buf: EQU $5C
C_IOD_Buf2: EQU %00000100 ; Output data Latch of PORTD bit2.
C_IOD_Buf1: EQU %00000010 ; Output data Latch of PORTD bit1.
C_IOD_Buf0: EQU %00000001 ; Output data Latch of PORTD bit0.
C_RAM_ADDR: EQU $60 ; RAM Start Address
C_STACK_BOTTOM: EQU $0FF ; Stack Bottom Address
CB_Bit7 EQU 7 ; for bit mode
CB_Bit6 EQU 6 ;
CB_Bit5 EQU 5 ;
CB_Bit4 EQU 4 ;
CB_Bit3 EQU 3 ;
CB_Bit2 EQU 2 ;
CB_Bit1 EQU 1 ;
CB_Bit0 EQU 0 ;
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