/* Copyright 1996, ESS Technology, Inc.					*//* SCCSID @(#)low.c	1.54 3/27/98 *//* * $Log$ */#include "mvd.h"#include "common.h"#include "util.h"#include "debug.h"#include "vcxi.h"#include "buffer.h"#include "low.h"#include "vp.h"#include "pts.h"#include "ioport.h"#include "constvar.h"#ifdef ECHO#include "echo.h"#endif#define PRINTF(a)/****************************************************************************** RDMA initialisation.******************************************************************************/void LOW_init_rdma(void){    RDMADoneMask = 0;    mvd[rdma_donemask] = RDMADoneMask;    mvd[rdma_done] = 0x3f;	/* Reset status flags */    mvd[rdma_transr_pri] = 0;    mvd[rdma_transr_cnt] = 0;    mvd[rdma_tdmw_pri] = 0;    mvd[rdma_tdmw_cnt] = 0;    mvd[rdma_gatewayr_pri] = 0;    mvd[rdma_gatewayr_cnt] = 0;    mvd[rdma_gatewayw_pri] = 0;    mvd[rdma_gatewayw_cnt] = 0;    mvd[rdma_hostr_pri] = 0;    mvd[rdma_hostr_cnt] = 0;    mvd[rdma_hostw_pri] = 0;    mvd[rdma_hostw_cnt] = 0;    mvd[rdma_tdmr_pri] = 0;    mvd[rdma_tdmr_cnt] = 0;    mvd[rdma_pageaddress] = 0;          /* locate to data segment */}/****************************************************************************** Gateway initialisation.******************************************************************************/#define B2RSTART     	0x00L#define B2REND     	(RiscFifoSize/2-1)#define R2BSTART   	(RiscFifoSize/2)#define R2BEND     	(RiscFifoSize-1)#define XPASTART	0x00L#define XPAEND		(XportFifoSize/2-1)#define XPVSTART	(XportFifoSize/2)#define XPVEND		(XportFifoSize-1)#define AHUFSTART	0x00#define VHUFSTART	(B2DFifoSize/4)#define AOUTSTART	(B2DFifoSize/2)#define HOUTSTART       (B2DFifoSize/2)#define AHUFEND    	(VHUFSTART-1)	#define VHUFEND		(AOUTSTART-1)	#define AOUTEND		(B2DFifoSize-1)#define HOUTEND         (B2DFifoSize-1)                #define AINSTART	0x00#define AINEND		(D2BFifoSize-1)/* address bits*/#define RiscFifo	5L#define XportFifo	7L#define D2BFifo		5L#define B2DFifo		6L/* ram size */#define RiscFifoSize		0x20L#define XportFifoSize		0x80L#define D2BFifoSize		0x20L#define B2DFifoSize		0x40L/* bits */#define gate_b2r_bit		0x00000001L#define gate_r2b_bit		0x00000002L#define gate_xportv_bit		0x00000004L#define gate_xporta_bit		0x00000008L#define gate_hufenc_bit		0x00000010L#define gate_audin_bit		0x00000020L#define gate_vhufdec_bit	0x00000040L#define gate_ahufdec_bit	0x00000080L#define gate_audout_bit		0x00000100L#define gata_hostout_bit 	0x00000200L#define gate_xa2_bit		gate_audin_bit#define gate_xa1_bit		gate_hufenc_bit#define gate_xa2_ff_vals	gate_audin_ff_vals#define gate_xa2_status		gate_audin_status#define gate_xa1_ff_vals	gate_hufenc_ff_vals#define gate_xa1_status		gate_hufenc_status/*RiscFifo	[r2b , b2r]XportFIFO	[xportv,xporta]Dma2BusFifo	[audin]Bus2DmaFifo 	[audout,ahufdec,vhufdec,hostout]*/#define enable_gateff(ch){					\	lwpoke(riface_irqsupress,0); asm("nop"); asm("nop");	\	gbl_gate_fiforeset &= ~cat3(gate_,ch,_bit);		\	lwpoke(gate_fiforeset,gbl_gate_fiforeset);		\}#define disable_gateff(ch){					\	lwpoke(riface_irqsupress,0); asm("nop"); asm("nop");	\	gbl_gate_fiforeset |= cat3(gate_,ch,_bit);		\	lwpoke(gate_fiforeset,gbl_gate_fiforeset);		\}#define set_gateff(ch,start,end,n) do {		\	lwpoke(cat3(gate_,ch,_ff_vals), 	\	((((end-start+1)/4-1) << (n<<1L)) 	\		| ((end) << n) 			\		| (start)			\	)); 					\} while (0)void LOW_init_gateway(void){    int	timeout;    gbl_gate_control = 0;    mvd[gate_control] = 0xfcL;			/* flush & reset all fifo */    mvd[gate_control] = gbl_gate_control;	/* flush end */    mvd[gate_fiforeset] = 0x3ff;		/* reset gateway fifo */    gbl_gate_fiforeset = 0x200;    set_gateff(r2b,	R2BSTART,  R2BEND,  RiscFifo);    set_gateff(b2r,	B2RSTART,  B2REND,  RiscFifo);    set_gateff(xporta,	XPASTART,  XPAEND,  XportFifo);    set_gateff(xportv,	XPVSTART,  XPVEND,  XportFifo);    set_gateff(audin,	AINSTART,  AINEND,  D2BFifo);    set_gateff(ahufdec, AHUFSTART, AHUFEND, B2DFifo);    set_gateff(vhufdec, VHUFSTART, VHUFEND, B2DFifo);    set_gateff(audioout,AOUTSTART, AOUTEND, B2DFifo);    mvd[gate_fiforeset] = gbl_gate_fiforeset;	/* unreset gateway fifo */} /****************************************************************************** DRAM related defines.******************************************************************************/#define DRAM_RFENBL		0x0200#define DRAM_CFG05		(0<<6)	/* .5 meg 1-256kx16 */#define DRAM_CFG1		(1<<6)	/* 1  meg 2-256kx16 */#define DRAM_CFG15		(2<<6)	#define DRAM_CFG2		(3<<6)	/* 2  meg 4-256kx16 */#define DRAM_CFG25		(4<<6)#define DRAM_CFG3		(5<<6)	#define DRAM_CFG4		(6<<6)	/* 4  meg 2-1megx16 */#define DRAM_CFG8		(7<<6)	/* 8  meg 4-1megx16 */#define DRAM_SPD2T3T3T	0x04#define DRAM_SPD2T2T3T	0x00#define DRAM_SPD3T3T3T  0x09#define NRSCR4TEN 0x6000  /* 0x6000 = enable 4t for noise reduction,			     0x2000 = enable 6t for nr */#define ENPRIODMA  0x20   /* Enable level priority and limit transfer block */ #ifndef DRAM_DMA_CNTL    /* Get rid of this item as soon as we use config file */#ifdef DVD_VCD#define DRAM_DMA_CNTL  (0xe01 | NRSCR4TEN | ENPRIODMA)/* edo , Stat3On , enable vpdma, endioOn, enable DMA level prior  */#else#ifdef MVD_BOARD#define DRAM_DMA_CNTL  (0xe01 | NRSCR4TEN | ENPRIODMA)/* edo , Stat3On , enable vpdma, endioOn, enable DMA level prior  */#else#define DRAM_DMA_CNTL  (0xe00 | NRSCR4TEN | ENPRIODMA | vcx_use_edo)/*       Stat3On , enable vpdma, endioOn, enable DMA level prior  */#endif#endif /* DVD_VCD */#endif #define DRAM_RESET_SCAL	0x080static int width3_shadow;/****************************************************************************** Buscon initialisation.******************************************************************************/void LOW_init_buscon(void){    mvd[gate_fiforeset] = 0x3ff;		/* reset gateway fifo */    mvd[buscon_vp_control] = 0;			/* reset on */    mvd[buscon_cmdque_clrhmode] = 0;		/* clr bits (blkdoneflag) */    mvd[buscon_cmdque_vpstatwait] = 0x0400;	/* clear endio */    mvd[buscon_cmdque_vpdmax] = 0x8000;		/* enable break */        mvd[buscon_dma_cntl] = DRAM_DMA_CNTL | 0x02;	/* reset dma */    mvd[buscon_dma_cntl] = DRAM_DMA_CNTL;    mvd[buscon_vp_control] = 0;			/* reset */    mvd[buscon_dma_disable] = x00ffffff;    mvd[buscon_dma_width0] = DMAWIDTH0;		/* whoever 512/4 */    mvd[buscon_dma_width1] = DMAWIDTH1;		/* UV 360/4 */    mvd[buscon_dma_width2] = DMAWIDTH2;		/* Y 720/4 & refresh */    width3_shadow = -1;}/************************************************************ * buscon related ************************************************************//************************************************************ * function: * width3 is a general purpose width for use like quant table, * mpgaudio, karaoke ... * the value of which should be loaded on the fly whenever it's used. * Altough mvd[buscon_dma_width3] is readable, we make a shadow to save * some code and time. ************************************************************/void LOW_set_buscon_dma_width3(ushort new_value){    assert(new_value < 0x200);    if (new_value != width3_shadow) {	VP_xfer_wait();	mvd[buscon_dma_width3] = new_value;	width3_shadow = new_value;    }}/****************************************************************************** Initiate DRAM refresh.******************************************************************************/void LOW_init_dram(void){#ifdef BUSCON_DRAM_CONTROL    /* For boards with special configuration specified in cfg file	*/    mvd[buscon_dram_control] = BUSCON_DRAM_CONTROL;#else#ifdef DVD_VCD    mvd[buscon_dram_control] = DRAM_RFENBL + DRAM_CFG2 + DRAM_SPD2T3T3T;#else#ifdef MPEG1#ifdef SVCD    mvd[buscon_dram_control] = DRAM_RFENBL + DRAM_CFG1 + DRAM_SPD2T3T3T;#else    /*     * The browser board can also be set to:     * mvd[buscon_dram_control] = DRAM_RFENBL + DRAM_CFG2 + DRAM_SPD3T3T3T;     */    mvd[buscon_dram_control] = DRAM_RFENBL + DRAM_CFG05 + DRAM_SPD2T3T3T;#endif#else    mvd[buscon_dram_control] = DRAM_RFENBL + DRAM_CFG3 + DRAM_SPD2T3T3T;#endif#endif /* DVD_VCD */#endif    /************************************************************    *    * For 3Mega Dram 729 times per 8ms .	    * New refresh period at 80MHz clk is    * 8ms/729 = (2048 -N* 8) * 12.5us    * N = 146d (0x92)    ************************************************************/    mvd[buscon_dram_reftime] = 0x92;	    /************************************************************    * deltas = ((0x80-dy)<<9) | (0x200 - dx);    * DeltaY=0,DeltaX=1    ************************************************************/    mvd[buscon_dma_deltas_ref] = (0x200 - 0x01);     /* use width0(256) for refresh */    mvd[buscon_dma_xpos_ref] = BDMA_WIDTH0+BDMA_INC2;    mvd[buscon_dma_ypos_ref] = 0x00;  }/****************************************************************************  Audio related.****************************************************************************/static int acnt0[3] = {0x620, 0x600, 0x400};	/* 44.1, 48 and 32 */static int acnt1[3] = {0x77a, 0x8d1, 0x6d1};#ifdef MPEG1static int pts_units_per_256_samples[3] = {261, 240, 360};#elsestatic int pts_units_per_256_samples[3] = {156734, 144000, 216000};#endif#ifdef DACLEFT				/* E.g. 1718			*/#define	FRAMEALIGN	0x40		/* Left justified		*/#else#define	FRAMEALIGN	0x80		/* Right justified		*/#endif#ifdef DACLAST#define	LASTBITLAST	0x2000		/* Last bit last		*/#else#define	LASTBITLAST	0		/* First bit first		*/#endif#ifdef INVATFS#define	ATFS_SETTING	0x20		/* Invert ATFS			*/#else	#define	ATFS_SETTING	0		/* Don't invert ATFS		*/#endif#ifdef SPDIFstatic int spdif_fs[3] = {0x00, 0x40, 0xc0};#endifvoid LOW_init_audio(void){    volatile int i;    gbl_gate_fiforeset &= ~gate_d2a_bit;    mvd[gate_fiforeset] = gbl_gate_fiforeset;    LOW_set_audio_sampling_frequency(0);#ifdef FS384    mvd[audioxmt] = 0x1118 | ATFS_SETTING | LASTBITLAST | FRAMEALIGN;#else#ifdef SPDIF    /* For MVD2 with 512FS */    mvd[audioxmt] = 0x0030 | FRAMEALIGN;#else    mvd[audioxmt] = 0x1018 | ATFS_SETTING | FRAMEALIGN;#endif#endif#ifdef ECHO    mvd[audiorcv] = 0x10a0;     /* MSB, sense on falling edge */    mvd[audioctl] = 0x0030;	/* external mclk */#else    mvd[audiorcv] = 0x00a8;#endif}void LOW_set_audio_sampling_frequency(int freq_code){    mvd[audiocnt0] = acnt0[freq_code];    mvd[audiocnt1] = acnt1[freq_code];    PTS_units_per_256_audio_samples = pts_units_per_256_samples[freq_code];#ifdef DVD_VCD 	/* fix it ASAP */    if (freq_code == 0) {	SET_AUX3; SET_AUX2;    } else if (freq_code == 1) {	CLEAR_AUX3; CLEAR_AUX2;    } else if (freq_code == 2) {	SET_AUX3; CLEAR_AUX2;    }#endif#ifdef SPDIF    {	int *cs8401a = (int *)0x14000100;	cs8401a[11] = spdif_fs[freq_code];    }#ifndef AUDIOCLK    if (freq_code == 0) {	TRISTATE_AUX3; SET_AUX2;    } else if (freq_code == 1) {	CLEAR_AUX3; CLEAR_AUX2;    } else if (freq_code == 2) {	SET_AUX3; CLEAR_AUX2;    }#endif#endif    prev_sampling_frequency = freq_code;}/****************************************************************************  Private DMA.****************************************************************************/#define pri_d2host	0x00000001#define pri_xax12d	0x00000002#define pri_d2ahuf	0x00000004#define pri_d2vhuf	0x00000008#define pri_aud2d	0x00000010#define pri_d2aud	0x00000020#define pri_d2tdm	0x00000040#define pri_xaud2d	0x00000080#define pri_xvid2d	0x00000100#define pri_ehuf2d  	0x00000200#define pri_xax22d	0x00000400#define pri_rst		0x00000800void LOW_init_private_dma(void){    int	private;    mvd[privatedmaenables] = pri_rst;    private = pri_xax12d | pri_xvid2d | pri_xaud2d | pri_d2ahuf | pri_d2vhuf;#ifdef ECHO    private |= pri_aud2d;#endif    private |= pri_d2aud;    mvd[privatedmaenables] = private;}/****************************************************************************  RISC interface. SRAM timing, timer, audio DAC etc.****************************************************************************/void LOW_init_riface(void){#ifndef MKROM    mvd[riface_width] = vcx_riface_width;     mvd[riface_wait_state] = vcx_riface_wait_state;#endif    mvd[riface_turnoff_delay] = vcx_riface_turnoff_delay;    mvd[riface_timer1] = 0;    mvd[riface_timer2] = 0;#ifdef PROBE_VP    mvd[riface_aux1] = 0x1b6;    shadow_riface_aux1 = 0x1b6;#else    mvd[riface_aux1] = 0x036;    shadow_riface_aux1 = 0x036;#endif}