/* Copyright 1996, ESS Technology, Inc.					*//* SCCSID @(#)ioport.h	1.13 5/4/98 *//* * $Log$ */#ifndef __IOPORT_H__#define __IOPORT_H__#include "mvd.h"GBLDEF_0(unsigned int shadow_riface_aux1, 0);GBLDEF_0(unsigned int shadow_riface_aux2, 0);/* * Since rfiace_ioport and riface_aux2 connect to pads, and read/write * to these ports get different values, we should NEVER directly write  * to these two registers. Instead, we should have two shadow variables  * to keep track of their current values. */#define	LOCK6		mvd[riface_irqsuppress] = (15 - 6)#define	LOCK9		mvd[riface_irqsuppress] = (15 - 9)#define	SET_AUX0	LOCK6; mvd[riface_aux1] = (shadow_riface_aux1 |= 1)#define	SET_AUX1	LOCK6; mvd[riface_aux1] = (shadow_riface_aux1 |= 2)#define	SET_AUX2	LOCK6; mvd[riface_aux1] = (shadow_riface_aux1 |= 0x14)#define	SET_AUX3	LOCK6; mvd[riface_aux1] = (shadow_riface_aux1 |= 0x28)#define	SET_AUX4	LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 |= 0x11)#define	SET_AUX5	LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 |= 0x44)#define	SET_AUX6	LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 |= 0x22)#define	SET_AUX7	LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 |= 0x88)#define	TRISTATE_AUX0	SET_AUX0#define	TRISTATE_AUX1	SET_AUX1#define	TRISTATE_AUX2	LOCK6; mvd[riface_aux1] = (shadow_riface_aux1 &= ~0x10)#define	TRISTATE_AUX3	LOCK6; mvd[riface_aux1] = (shadow_riface_aux1 &= ~0x20)#define	TRISTATE_AUX4	LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 &= ~0x10)#define	TRISTATE_AUX5	LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 &= ~0x40)#define	TRISTATE_AUX6	LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 &= ~0x20)#define	TRISTATE_AUX7	LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 &= ~0x80)#define	CLEAR_AUX0	LOCK6; mvd[riface_aux1] = (shadow_riface_aux1 &= ~1)#define	CLEAR_AUX1	LOCK6; mvd[riface_aux1] = (shadow_riface_aux1 &= ~2)#define	CLEAR_AUX2	LOCK9; shadow_riface_aux1&= ~4;			\			mvd[riface_aux1]  = (shadow_riface_aux1 |= 0x10)#define	CLEAR_AUX3	LOCK9; shadow_riface_aux1&= ~8;			\			mvd[riface_aux1]  = (shadow_riface_aux1 |= 0x20)#define	CLEAR_AUX4	LOCK9; shadow_riface_aux2 &= ~1;		\			mvd[riface_aux2]   = (shadow_riface_aux2|= 0x10)#define	CLEAR_AUX5	LOCK9; shadow_riface_aux2 &= ~4;		\			mvd[riface_aux2]   = (shadow_riface_aux2|= 0x40)#define	CLEAR_AUX6	LOCK9; shadow_riface_aux2 &= ~2;		\			mvd[riface_aux2]   = (shadow_riface_aux2|= 0x20)#define	CLEAR_AUX7	LOCK9; shadow_riface_aux2 &= ~8;		\			mvd[riface_aux2]   = (shadow_riface_aux2|= 0x80)/* * 3208/3210 has built in XOR. One of the inputs to the XOR gate is the * output data of AUX4 (regardless of the state of the tri-state control). * Therefore, writing a 1 to the data is equivalent to setting the input * 1. * * When we change this input, most likely we also want to disable the * tri-state so the signal does not go off chip. */#if (!CUST6 && !TVM_MODULE)#define	SET_IRXOR	LOCK9; shadow_riface_aux2 &= ~0x10;		\			mvd[riface_aux2]  = (shadow_riface_aux2 |= 0x01)#define	CLEAR_IRXOR	LOCK6; mvd[riface_aux2] = (shadow_riface_aux2 &= ~0x11)#define	IS_IRXOR_HIGH	((shadow_riface_aux2 & 0x1) ? 1 : 0)#endif /* !CUST6 and !TVM_MODULE */#define	AUX0_HIGH	(mvd[riface_aux1] & 0x1)#define	AUX1_HIGH	(mvd[riface_aux1] & 0x2)#define	AUX2_HIGH	(mvd[riface_aux1] & 0x4)#define	AUX3_HIGH	(mvd[riface_aux1] & 0x8)#define	AUX4_HIGH	(mvd[riface_aux2] & 0x1)#define	AUX5_HIGH	(mvd[riface_aux2] & 0x4)#define	AUX6_HIGH	(mvd[riface_aux2] & 0x2)#define	AUX7_HIGH	(mvd[riface_aux2] & 0x8)#define	AUX0_LOW	(!AUX0_HIGH)#define	AUX1_LOW	(!AUX1_HIGH)#define	AUX2_LOW	(!AUX2_HIGH)#define	AUX3_LOW	(!AUX3_HIGH)#define	AUX4_LOW	(!AUX4_HIGH)#define	AUX5_LOW	(!AUX5_HIGH)#define	AUX6_LOW	(!AUX6_HIGH)#define	AUX7_LOW	(!AUX7_HIGH)#endif /* __IOPORT_H__ */