library verilog;use verilog.vl_types.all;entity acs4 is    port(        y2_s1           : in     vl_logic;        y1_s1           : in     vl_logic;        sel_initial_s1  : in     vl_logic;        decisions_s1    : out    vl_logic_vector(3 downto 0);        path_metrics_s1 : out    vl_logic_vector(15 downto 0);        phi1            : in     vl_logic;        phi2            : in     vl_logic    );end acs4;