library verilog;use verilog.vl_types.all;entity acs1 is    port(        phi1            : in     vl_logic;        phi2            : in     vl_logic;        path_metric0_s1 : in     vl_logic_vector(3 downto 0);        path_metric1_s1 : in     vl_logic_vector(3 downto 0);        branch_metric0_s1: in     vl_logic_vector(1 downto 0);        branch_metric1_s1: in     vl_logic_vector(1 downto 0);        path_metric_out_s1: out    vl_logic_vector(3 downto 0);        decision_s1     : out    vl_logic;        sel_initial_s1  : in     vl_logic;        initial_metric_s1: in     vl_logic_vector(3 downto 0)    );end acs1;