library verilog;use verilog.vl_types.all;entity chip_core is    port(        sync_s1         : in     vl_logic;        self_test_s1    : in     vl_logic;        external_y_s1   : in     vl_logic_vector(1 downto 0);        orig_del_bit_s1 : out    vl_logic;        fail_s1         : out    vl_logic;        data_valid_s1   : out    vl_logic;        decoded_bit_s1  : out    vl_logic;        decoded_column_s1: out    vl_logic_vector(3 downto 0);        decisions_s1    : out    vl_logic_vector(3 downto 0);        path_metrics_s1 : out    vl_logic_vector(15 downto 0);        phi1            : in     vl_logic;        phi2            : in     vl_logic    );end chip_core;