?? sub.asm
字號:
.mmregs
.include c54.inc
.def timer0,hpisys,progflash
.ref ss,class,add_h,add_l,end_flg,run_flg,add_start,buf,check
.ref io_map,page,sec,progadd,flashadd,data_h,data_l
.sect "progsys"
*************************** timer0 ***************************
timer0:
PSHM AL
PSHM AH
PSHM AG
PSHM AR2
STM ss,AR2
ADDM #1,*AR2
LD *AR2,A
BC timer0exit,ANEQ
ST -1000,*AR2 ;-3096
LDM ST1,A
XOR #0x2000,A
STLM A,ST1
timer0exit:
POPM AR2
POPM AG
POPM AH
POPM AL
RET
************************** hpisys ******************************
hpisys:
PSHM AL
PSHM AH
PSHM AG
PSHM AR2
RSBX SXM
STM class ,AR2
CMPM *AR2,#0x55
BC progwr,TC
CMPM *AR2,#0xaa
BC progrd,TC
CMPM *AR2,#0x33
BC datawr,TC
CMPM *AR2,#0xcc
BC datard,TC
CMPM *AR2,#0x55aa
BC runflash,TC
CMPM *AR2,#0xaa55
BC progflash,TC
B exit
*
progwr:
LDM ST1,A
AND #0xDFFF,A
STLM A,ST1
STM end_flg,AR2
NOP
NOP
CMPM *AR2,#0x55AA
NOP
NOP
BC progwr1,TC
NOP
NOP
STM run_flg,AR2
NOP
NOP
CMPM *AR2,#0x55AA
NOP
NOP
BC progwr3,TC
NOP
NOP
B progwr
progwr1:
; ________________________ write ___________________
STM add_h,AR2
LD *AR2+,16,A
ADD *AR2+,A
STM buf,AR2
RPT #(256-1)
WRITA *AR2+
; _________________________ read ____________________
STM add_h,AR2
LD *AR2+,16,A
ADD *AR2+,A
STM buf,AR2
RPT #(256-1)
READA *AR2+
; _______________________ check _____________________
STM buf,AR2
LD #0,A
RPT #(256-1)
XOR *AR2+,A
STL A,*(check)
; _______________________ set flg ____________________
ST #0,*(end_flg)
STM run_flg,AR2
CMPM *AR2,#0
BC progwr,TC
; _________________________ run ______________________
progwr3:
STM #0,XPC
STM add_start,AR2
NOP
NOP
LD *AR2,A
NOP
NOP
BACC A ;goto progRAM
nop
nop
B exit
*
***************************** progrd **********************
progrd:
STM add_h,AR2
LD *AR2+,16,A
ADD *AR2,A
STM #0x3030,AR2
RPT #(256-1)
READA *AR2+
ST #0,*(class)
STM #0xabc0,AR2
LD *AR2,A
B exit
*
************************** datawr **************************
datawr:
LDM ST1,A
OR #0x2000,A
* AND #0xDFFF,A
STLM A,ST1
STM end_flg,AR2
NOP
NOP
CMPM *AR2,#0x55AA
NOP
NOP
BC datawr1,TC
NOP
NOP
STM run_flg,AR2
NOP
NOP
CMPM *AR2,#0x55AA
NOP
NOP
BC exit,TC
NOP
NOP
B datawr
datawr1:
;write
* STM add_h,AR2
MVDM add_l,AR2
RPT #(256-1)
MVKD buf,*AR2+
;read
MVDM add_l,AR2
RPT #(256-1)
MVDK *AR2+,buf
;check
STM buf,AR2
LD #0,A
RPT #(256-1)
XOR *AR2+,A
STL A,*(check)
;set flg
ST #0,*(end_flg)
B datawr ;Goto datawr
*
***************************** datard **********************
datard:
MVDM add_l,AR2
RPT #(256-1)
MVDK *AR2+,buf
ST #0,*(class)
B exit
*
************************* Program Flash *******************
progflash:
RSBX XF
STM #0,CLKMD
clk40: LDM CLKMD,A
AND #0x01,A
BC clk40,ANEQ
STM #0x03ff,CLKMD ;PLL=1 MUL=2 40Mhz
;-------------------------- ChipErase ---------------------
ST #0x100,*(io_map)
PORTW *(io_map),0xbfff
nop
nop
ST #0xaa,*(io_map)
PORTW *(io_map),0xd555 ;AAH--->5555H
ST #0,*(io_map)
PORTW *(io_map),0xbfff
nop
nop
ST #0x55,*(io_map)
PORTW *(io_map),0xeaaa ;55H--->2AAAH
ST #0x100,*(io_map)
PORTW *(io_map),0xbfff
nop
nop
ST #0x80,*(io_map)
PORTW *(io_map),0xd555 ;80H--->5555H
ST #0x100,*(io_map)
PORTW *(io_map),0xbfff
nop
nop
ST #0xaa,*(io_map)
PORTW *(io_map),0xd555 ;AAH--->5555H
ST #0,*(io_map)
PORTW *(io_map),0xbfff
nop
nop
ST #0x55,*(io_map)
PORTW *(io_map),0xeaaa ;55H--->2AAAH
ST #0x100,*(io_map)
PORTW *(io_map),0xbfff
nop
nop
ST #0x10,*(io_map)
PORTW *(io_map),0xd555 ;10H--->5555H
STM #200,AR1
WR_loop:
RPT #(50000-1)
NOP
BANZ WR_loop,*AR1-
;-------------------------- ChipProg ---------------------
ST #0,*(page)
ST #0,*(sec)
STM #(4-1),AR3
WR_page:
STM #(4-1),AR4
ST #0x8000,*(progadd)
WR_sec:
STM #(8192-1),AR7
ST #0xc000,*(flashadd)
WR_byte:
LD *(page),16,A
ADD *(progadd),A
READA *(data_l)
LD *(data_l),A
ANDM #0xff,*(data_l)
STL A,-8,*(data_h)
ST #0x100,*(io_map)
PORTW *(io_map),0xbfff
nop
nop
ST #0xaa,*(io_map)
PORTW *(io_map),0xd555 ;AAH--->5555H
ST #0,*(io_map)
PORTW *(io_map),0xbfff
nop
nop
ST #0x55,*(io_map)
PORTW *(io_map),0xeaaa ;55H--->2AAAH
ST #0x100,*(io_map)
PORTW *(io_map),0xbfff
nop
nop
ST #0xa0,*(io_map)
PORTW *(io_map),0xd555 ;A0H--->5555H
PORTW *(sec),0xbfff
nop
nop
MVDP *(flashadd),#(WR_hw+2)
MVDP *(flashadd),#(WR_hr+2)
LD *(flashadd),A
ADD #1,A
STL A,*(flashadd)
WR_hw:
PORTW *(data_h),0xc000
RPT #(1000-1)
NOP
WR_hr:
PORTR 0xc000,*(io_map)
LD *(io_map),A
XOR *(data_h),A
AND #0x80,A
BC WR_hr,ANEQ
ST #0x100,*(io_map)
PORTW *(io_map),0xbfff
nop
nop
ST #0xaa,*(io_map)
PORTW *(io_map),0xd555 ;AAH--->5555H
ST #0,*(io_map)
PORTW *(io_map),0xbfff
nop
nop
ST #0x55,*(io_map)
PORTW *(io_map),0xeaaa ;55H--->2AAAH
ST #0x100,*(io_map)
PORTW *(io_map),0xbfff
nop
nop
ST #0xa0,*(io_map)
PORTW *(io_map),0xd555 ;A0H--->5555H
PORTW *(sec),0xbfff
nop
nop
MVDP *(flashadd),#(WR_lw+2)
MVDP *(flashadd),#(WR_lr+2)
LD *(flashadd),A
ADD #1,A
STL A,*(flashadd)
WR_lw:
PORTW *(data_l),0xc000
RPT #(1000-1)
NOP
WR_lr:
PORTR 0xc000,*(io_map)
LD *(io_map),A
XOR *(data_l),A
AND #0x80,A
BC WR_lr,ANEQ
LD *(progadd),A
ADD #1,A
STL A,*(progadd)
BANZ WR_byte,*AR7-
ADDM #0x100,*(sec)
BANZ WR_sec,*AR4-
ADDM #1,*(page)
BANZ WR_page,*AR3-
STM #0,CLKMD
clk100: LDM CLKMD,A
AND #0x01,A
BC clk100,ANEQ
STM #0x43ff,CLKMD ;PLL=4 MUL=5 100Mhz
B exit
*
************************* From Flash Run *******************
runflash:
RSBX XF
STM #0,CLKMD
fclk40: LDM CLKMD,A
AND #0x01,A
BC fclk40,ANEQ
STM #0x03ff,CLKMD ;PLL=1 MUL=2 40Mhz
ST #0,*(page)
ST #0,*(sec)
STM #(4-1),AR3
RD_page:
ST #0x8000,*(progadd)
STM #(4-1),AR4
RD_sec:
ST #0xc000,*(flashadd)
STM #(8192-1),AR7
PORTW *(sec),0xbfff
nop
nop
RD_byte:
MVDP *(flashadd),#(RD_h+2)
RD_h:
PORTR 0xc000,*(data_h)
ANDM #0xff,*(data_h)
LD *(flashadd),A
ADD #1,A
STL A,*(flashadd)
MVDP *(flashadd),#(RD_l+2)
RD_l:
PORTR 0xc000,*(data_l)
ANDM #0xff,*(data_l)
LD *(flashadd),A
ADD #1,A
STL A,*(flashadd)
LD *(data_h),8,A
ADD *(data_l),A
STL A,*(data_l)
LD *(page),16,A
ADD *(progadd),A
WRITA *(data_l)
LD *(progadd),A
ADD #1,A
STL A,*(progadd)
BANZ RD_byte,*AR7-
ADDM #0x100,*(sec)
BANZ RD_sec,*AR4-
ADDM #1,*(page)
BANZ RD_page,*AR3-
STM #0,CLKMD
fclk100:
LDM CLKMD,A
AND #0x01,A
BC fclk100,ANEQ
STM #0x43ff,CLKMD ;PLL=4 MUL=5 100Mhz
B 0xa000
exit: SSBX SXM
POPM AR2
POPM AG
POPM AH
POPM AL
RET
.end
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