{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version " "Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jul 26 17:01:31 2004 " "Info: Processing started: Mon Jul 26 17:01:31 2004" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off ram44 -c ram44 " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off ram44 -c ram44" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "D:/workspace/dsp-d/ram/ram44.bdf" "" "" { Schematic "D:/workspace/dsp-d/ram/ram44.bdf" { { 112 32 200 128 "clk" "" } } } } { "e:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register ram:inst1\|data3\[3\] ram:inst1\|q\[3\]~reg0 200.0 MHz Internal " "Info: Clock clk Internal fmax is restricted to 200.0 MHz between source register ram:inst1\|data3\[3\] and destination register ram:inst1\|q\[3\]~reg0" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.5 ns 2.5 ns 5.0 ns " "Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.200 ns + Longest register register " "Info: + Longest register to register delay is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram:inst1\|data3\[3\] 1 REG LC3_A28 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_A28; Fanout = 1; REG Node = 'ram:inst1\|data3\[3\]'" {  } { { "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" Compiler "ram44" "UNKNOWN" "V1" "D:/workspace/dsp-d/ram/db/ram44.quartus_db" { Floorplan "" "" "" { ram:inst1|data3[3] } "NODE_NAME" } } } { "D:/workspace/dsp-d/ram/ram.vhd" "" "" { Text "D:/workspace/dsp-d/ram/ram.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 1.900 ns ram:inst1\|i~666 2 COMB LC5_A28 1 " "Info: 2: + IC(0.300 ns) + CELL(1.600 ns) = 1.900 ns; Loc. = LC5_A28; Fanout = 1; COMB Node = 'ram:inst1\|i~666'" {  } { { "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" Compiler "ram44" "UNKNOWN" "V1" "D:/workspace/dsp-d/ram/db/ram44.quartus_db" { Floorplan "" "" "1.900 ns" { ram:inst1|data3[3] ram:inst1|i~666 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.000 ns) 3.200 ns ram:inst1\|q\[3\]~reg0 3 REG LC1_A28 7 " "Info: 3: + IC(0.300 ns) + CELL(1.000 ns) = 3.200 ns; Loc. = LC1_A28; Fanout = 7; REG Node = 'ram:inst1\|q\[3\]~reg0'" {  } { { "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" Compiler "ram44" "UNKNOWN" "V1" "D:/workspace/dsp-d/ram/db/ram44.quartus_db" { Floorplan "" "" "1.300 ns" { ram:inst1|i~666 ram:inst1|q[3]~reg0 } "NODE_NAME" } } } { "D:/workspace/dsp-d/ram/ram.vhd" "" "" { Text "D:/workspace/dsp-d/ram/ram.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 81.25 % " "Info: Total cell delay = 2.600 ns ( 81.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 18.75 % " "Info: Total interconnect delay = 0.600 ns ( 18.75 % )" {  } {  } 0}  } { { "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" Compiler "ram44" "UNKNOWN" "V1" "D:/workspace/dsp-d/ram/db/ram44.quartus_db" { Floorplan "" "" "3.200 ns" { ram:inst1|data3[3] ram:inst1|i~666 ram:inst1|q[3]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.500 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 7.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns clk 1 CLK Pin_101 20 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_101; Fanout = 20; CLK Node = 'clk'" {  } { { "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" Compiler "ram44" "UNKNOWN" "V1" "D:/workspace/dsp-d/ram/db/ram44.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/workspace/dsp-d/ram/ram44.bdf" "" "" { Schematic "D:/workspace/dsp-d/ram/ram44.bdf" { { 112 32 200 128 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(0.000 ns) 7.500 ns ram:inst1\|q\[3\]~reg0 2 REG LC1_A28 7 " "Info: 2: + IC(2.600 ns) + CELL(0.000 ns) = 7.500 ns; Loc. = LC1_A28; Fanout = 7; REG Node = 'ram:inst1\|q\[3\]~reg0'" {  } { { "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" Compiler "ram44" "UNKNOWN" "V1" "D:/workspace/dsp-d/ram/db/ram44.quartus_db" { Floorplan "" "" "2.600 ns" { clk ram:inst1|q[3]~reg0 } "NODE_NAME" } } } { "D:/workspace/dsp-d/ram/ram.vhd" "" "" { Text "D:/workspace/dsp-d/ram/ram.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.900 ns 65.33 % " "Info: Total cell delay = 4.900 ns ( 65.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 34.67 % " "Info: Total interconnect delay = 2.600 ns ( 34.67 % )" {  } {  } 0}  } { { "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" Compiler "ram44" "UNKNOWN" "V1" "D:/workspace/dsp-d/ram/db/ram44.quartus_db" { Floorplan "" "" "7.500 ns" { clk ram:inst1|q[3]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.500 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 7.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns clk 1 CLK Pin_101 20 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = Pin_101; Fanout = 20; CLK Node = 'clk'" {  } { { "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" Compiler "ram44" "UNKNOWN" "V1" "D:/workspace/dsp-d/ram/db/ram44.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/workspace/dsp-d/ram/ram44.bdf" "" "" { Schematic "D:/workspace/dsp-d/ram/ram44.bdf" { { 112 32 200 128 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(0.000 ns) 7.500 ns ram:inst1\|data3\[3\] 2 REG LC3_A28 1 " "Info: 2: + IC(2.600 ns) + CELL(0.000 ns) = 7.500 ns; Loc. = LC3_A28; Fanout = 1; REG Node = 'ram:inst1\|data3\[3\]'" {  } { { "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" Compiler "ram44" "UNKNOWN" "V1" "D:/workspace/dsp-d/ram/db/ram44.quartus_db" { Floorplan "" "" "2.600 ns" { clk ram:inst1|data3[3] } "NODE_NAME" } } } { "D:/workspace/dsp-d/ram/ram.vhd" "" "" { Text "D:/workspace/dsp-d/ram/ram.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.900 ns 65.33 % " "Info: Total cell delay = 4.900 ns ( 65.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 34.67 % " "Info: Total interconnect delay = 2.600 ns ( 34.67 % )" {  } {  } 0}  } { { "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" Compiler "ram44" "UNKNOWN" "V1" "D:/workspace/dsp-d/ram/db/ram44.quartus_db" { Floorplan "" "" "7.500 ns" { clk ram:inst1|data3[3] } "NODE_NAME" } } }  } 0}  } { { "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" Compiler "ram44" "UNKNOWN" "V1" "D:/workspace/dsp-d/ram/db/ram44.quartus_db" { Floorplan "" "" "7.500 ns" { clk ram:inst1|q[3]~reg0 } "NODE_NAME" } } } { "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" Compiler "ram44" "UNKNOWN" "V1" "D:/workspace/dsp-d/ram/db/ram44.quartus_db" { Floorplan "" "" "7.500 ns" { clk ram:inst1|data3[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "D:/workspace/dsp-d/ram/ram.vhd" "" "" { Text "D:/workspace/dsp-d/ram/ram.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "D:/workspace/dsp-d/ram/ram.vhd" "" "" { Text "D:/workspace/dsp-d/ram/ram.vhd" 15 -1 0 } }  } 0}  } { { "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" Compiler "ram44" "UNKNOWN" "V1" "D:/workspace/dsp-d/ram/db/ram44.quartus_db" { Floorplan "" "" "3.200 ns" { ram:inst1|data3[3] ram:inst1|i~666 ram:inst1|q[3]~reg0 } "NODE_NAME" } } } { "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" Compiler "ram44" "UNKNOWN" "V1" "D:/workspace/dsp-d/ram/db/ram44.quartus_db" { Floorplan "" "" "7.500 ns" { clk ram:inst1|q[3]~reg0 } "NODE_NAME" } } } { "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" Compiler "ram44" "UNKNOWN" "V1" "D:/workspace/dsp-d/ram/db/ram44.quartus_db" { Floorplan "" "" "7.500 ns" { clk ram:inst1|data3[3] } "NODE_NAME" } } }  } 0}  } { { "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" "" "" { Report "D:/workspace/dsp-d/ram/db/ram44_cmp.qrpt" Compiler "ram44" "UNKNOWN" "V1" "D:/workspace/dsp-d/ram/db/ram44.quartus_db" { Floorplan "" "" "" { ram:inst1|q[3]~reg0 } "NODE_NAME" } } } { "D:/workspace/dsp-d/ram/ram.vhd" "" "" { Text "D:/workspace/dsp-d/ram/ram.vhd" 15 -1 0 } }  } 0}