LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY ram IS
PORT(clk,wr,rd,rst:in std_logic;
     a:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
     d:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
     q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END;
ARCHITECTURE BEHAV OF ram IS
signal data0,data1,data2,data3:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
process(clk,rst)
begin
  if rst='1' then 
      data0<=(others=>'0');
      data1<=(others=>'0');
      data2<=(others=>'0');
      data3<=(others=>'0');
   elsif (clk'event and clk='1') then
       if ((wr='1') and (rd='0'))  then
          case a is 
            when "00"=>data0<=d;
            when "01"=>data1<=d;
            when "10"=>data2<=d;
            when "11"=>data3<=d;
            when others=>null; 
          end case;                  
       elsif((wr='0') and (rd='1'))  then
          case a is 
            when "00"=>q<=data0;
            when "01"=>q<=data1;
            when "10"=>q<=data2;
            when "11"=>q<=data3;
            when others=>null; 
          end case;
       end if;
   end if;    
end process;   
END;