.extern main	

	.text
	.global _start
_start:
	la r28,_gp
//Interrupt enable
     li r4, 0x1
	mtcr r4, cr0
	nop
	nop
	nop
	nop
	nop

//change exception vector base to 0xa0000000
    li r4, 0xa0000000
	mtcr r4, cr3

//LDM enable
	li    r5,  0x8a000000	//The start address of data segment will move to LDM
	cache 0xb, [r5,0]	//The size of data segment will move to LDM(4k byte)
	mfcr  r11, cr4
	ori   r11, 0x8		// Enable LDM bit(bit 3) of CCR4
	mtcr  r11, cr4		// Enable LDM bit(bit 3) of CCR4 (W-Sttage)
	nop
	nop
	nop
	nop
	nop
	nop

	la r8,__bss_start
	la r9,_bss_end__
	li r10, 0
next_byte:
	sb    r10,[r8]+,1
	cmp.c r8,r9
	ble   	next_byte

	la r0,_stack

/* // Enable Write back data cache
	la	r4, wback_en
wback_en:
	cache	0x1d, [r4, 0]
*/
// Enable BIU Write buffer
	la	r4, biu_wben
biu_wben:
	cache	0x1b, [r4, 0]
 
	jl	main
infinte_loop:
	b infinte_loop



	.global _main
_main:
	br r3

	.global __main
__main:
	br r3
/*
.section .exit,"ax"
	.global exit
exit:
	la	r4, exit	
	br	r4
	br r3

.section .abort,"ax"
	.global abort
abort:
	la	r4, abort	
	br	r4
	br r3
*/