/******************************************************************************
 *
 *     The information contained herein is the exclusive property of
 *   Sunplus Technology Co. And shall not be distributed, reproduced,
 *   or disclosed in whole in part without prior written permission.
 *
 *         (C) COPYRIGHT 2005   SUNPLUS TECHNOLOGY CO.
 *                        ALL RIGHTS RESERVED
 *
 * The entire notice above must be reproduced on all authorized copies.
 *
 *****************************************************************************/

/******************************************************************************
 *  Filename:   	CE_Show.c
 *  Author:     	Robin.xjliu  (eMail: xjliu@sunplus.com)
 *  Tel:        	00885-028-87848688-5884
 *  Date:       	2005-11-05
 *  Description:	project entry
 *  Reference:
 *  Version history:
 *-----------------------------------------------------------------------------
 *	Version   YYYY-MM-DD-INDEX   Modified By         Description
 *	1.0.0     2005-11-05           xjliu               Create
 *
 *****************************************************************************/
#include "CE_Show.h"

void InitSPG290(U32 miu_mp4_clock_ratio)
{
	unsigned int *port;
	unsigned int i;
	port = (unsigned int *)0x88210038;	*port = 0x00000002;		// cpu clk / 3
	
	// MP4
	port = (unsigned int *)0x88210140;	*port = 0x00000003;		// P_CKG_CFG_BUFCTRL Enable
	port = (unsigned int *)0x882100f0;	*port = miu_mp4_clock_ratio-1;//0:1:1;(1:MIU_CLK 2:MP4_CLK 1)
	port = (unsigned int *)0x882100ec;	*port = 0x00000007;		
	
	
	port = (unsigned int *)0x88210024;	*port = 0x00000000;		// PPU Clock = 40.5 MHz
	port = (unsigned int *)0x88210020;	*port = 0x00000003;		// PPU Clock Enable
	port = (unsigned int *)0x882100C8;	*port = 0x00000003;		// BUF Control Enable
	port = (unsigned int *)0x8809004c;	*port = 0x00000001;		// BUF Control Interrupt Mask
	
	port = (unsigned int *)0x882100FC;  *port = 0x00000003;		// SFTCFG Clock Enable
	// mp4
 	if(miu_mp4_clock_ratio==1)		
		*P_SYS_C2M_STBLENG=0x00000006;//SFTCFG
	else if(miu_mp4_clock_ratio==2)	
		*P_SYS_C2M_STBLENG=0x0000000a;//SFTCFG
	else if(miu_mp4_clock_ratio==3)	
		*P_SYS_C2M_STBLENG=0x0000000f;//SFTCFG
 	

	port = (unsigned int *)0x88210034;	*port = 0x00000003;		// en lcd clk
	port = (unsigned int *)0x88200000;	*port = 0x00000002;		// LCD pin mux		
		
	port = (unsigned int *)0x88200004;	*port = 0x00000001;		// SFTCFG Select I2C
	port = (unsigned int *)0x88200000;	*port |= 0x00000300;	// SFTCFG Select CCIR656
	port = (unsigned int *)0x88210018;	*port = 0x00000003;		// CSI Clock Enable
	port = (unsigned int *)0x8821001C;  *port = 0x00000008;		// Pixel Clock Enable
	port = (unsigned int *)0x88210094;  *port = 0x00000003;     // I2C Clock Enable
	port = (unsigned int *)0x88210050;	*port = 0x00000003;		// BLNDMA Clock Enable
	port = (unsigned int *)0x882100CC;  *port = 0x00000003;		// LDMDMA Clock Enable
	port = (unsigned int *)0x880a0020;	*port = 0x00000000;		// IRQ Mask Enable
	port = (unsigned int *)0x880a0024;	*port = 0x00000000;		// IRQ Mask Enable
	
	port = (unsigned int *)0x88210030;	*port = 0x00000003;		// TVE Clock Enable
	port = (unsigned int *)0x88030050;	*port = 0x00000000;		// Video DAC Enable
	
	port = (unsigned int *)0x882100A4;  *port = 0x00000003;		// SDCard Clock Enable
	port = (unsigned int *)0x88210098;	*port = 0x00000003;		// SPI Clock Enable
	port = (unsigned int *)0x88210058;  *port = 0x00000003;     // APBDMA Clock Enable
		
	port = (unsigned int *)0x8821005C;	*port = 0x00000003;		// UART Clock Enable
	
	port = (unsigned int *)0x88200030;  *port = 0xf819f819;		// P_NFLASH_GPIO_PUPD for SDCard Setting	
	
	port = (unsigned int *)0x882000A4; 	*port = 0x00010100;		// SFTCFG SDCard Enable & SPI Enable
	
	port = (unsigned int *)0x8821003C;	*port = 0x00000003;		// SPU Clock Enable 
	
	port = (unsigned int *)0x882100AC;	*port = 0x00000003;		// ADC Clock Enable
	// Tested by Bruce
	*P_CKG_CFG_PLLA = 0x00000007; // enable audio pll
	*P_CKG_CFG_SFT = 0x00000003;
	*P_CKG_CFG_ADC = 0x00000003; // adc controller clock enable
	*P_CKG_SEL_ADC = 0x00000001; // adc source clock div 2	
	//	print1("SPU Clock Enabled\n");
	port = (unsigned int *)0x88051474;	*port = 0xFFFFFFFE;		// DAC output Enable
	for(i=0;i<200000;i++)						// Delay between enabling CEN and OEN, at least 30ms
	{}
	
	port = (unsigned int *)0x88051474;	*port = 0xFFFFFFFC;		// DAC output Enable
	for(i=0;i<200000;i++)						// Delay for DAC stablization
	{}
}

extern GAMESTATE BW_PlayMP4(void);

int main(void)
{
	InitSPG290(2);
	
	BW_Main();
	return 0;
}