`timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////// Company: // Engineer: // // Create Date:    22:35:42 11/21/2006 // Design Name: // Module Name:    ccmul // Project Name: // Target Devices: // Tool versions: // Description: //// Dependencies: //// Revision: // Revision 0.01 - File Created// Additional Comments: ////////////////////////////////////////////////////////////////////////////////////`include "sub1.v" `include "mult.v" `include "add.v"`include "sub2.v" module ccmul(clk, x_in, y_in, c_in, cps_in, cms_in, r_out, i_out);	 parameter w2=21,w1=11,w=10;	 input clk;    input[w-1:0] x_in,y_in,c_in;    input [w1-1:0] cps_in,cms_in;    output[w-1:0] r_out,i_out;	 reg [w-1:0] r_out,i_out;    wire [w-1:0] x,y,c;    wire [w2-1:0] r,i,cmsy,cpsx,xmyc,sum;    wire [w1-1:0] xmy,cps,cms,sxtx,sxty;	 assign x=x_in;	 assign y=y_in;	 assign c=c_in;	 assign cps=cps_in;	 assign cms=cms_in;	 always@(posedge clk)	 begin	 r_out<=r[w2-2:w];	 i_out<=i[w2-2:w];	 end	 assign sxtx={x[w-1],x};	 assign sxty={y[w-1],y};	 sub1 sub_1 (.dataa(sxtx),.datab(sxty),.result(xmy));mult mult_1 (.dataa(xmy),.datab(c),.result(xmyc));mult mult_2 (.dataa(cms),.datab(y),.result(cmsy));mult mult_3 (.dataa(cps),.datab(x),.result(cpsx));add add_1(.dataa(cmsy),.datab(xmyc),.result(r));sub2 sub_2(.dataa(cpsx),.datab(xmyc),.result(i));endmodule