////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 8.1i
//  \   \         Application : ISE
//  /   /         Filename : test.ant
// /___/   /\     Timestamp : Thu Mar 15 21:46:00 2007
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: 
//Design Name: test
//Device: Xilinx
//
`timescale 1ns/1ps

module test;
    reg [7:0] Aim_in = 8'b00000000;
    reg [7:0] Are_in = 8'b00000000;
    reg [7:0] Bim_in = 8'b00000000;
    reg [7:0] Bre_in = 8'b00000000;
    reg clk = 1'b0;
    reg [8:0] cms_in = 9'b000000000;
    reg [8:0] cps_in = 9'b000000000;
    reg [7:0] c_in = 8'b00001000;
    wire [7:0] Dim_out;
    wire [7:0] Dre_out;
    wire [7:0] Eim_out;
    wire [7:0] Ere_out;

    parameter PERIOD = 200;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 0;

    initial    // Clock process for clk
    begin
        #OFFSET;
        forever
        begin
            clk = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
            #(PERIOD*DUTY_CYCLE);
        end
    end

    lian UUT (
        .Aim_in(Aim_in),
        .Are_in(Are_in),
        .Bim_in(Bim_in),
        .Bre_in(Bre_in),
        .clk(clk),
        .cms_in(cms_in),
        .cps_in(cps_in),
        .c_in(c_in),
        .Dim_out(Dim_out),
        .Dre_out(Dre_out),
        .Eim_out(Eim_out),
        .Ere_out(Ere_out));

    integer TX_FILE = 0;
    integer TX_ERROR = 0;
    
    initial begin    // Annotation process for clock clk
        #0;
        ANNOTATE_Dim_out;
        ANNOTATE_Dre_out;
        ANNOTATE_Eim_out;
        ANNOTATE_Ere_out;
        #OFFSET;
        forever begin
            #115;
            ANNOTATE_Dim_out;
            ANNOTATE_Dre_out;
            ANNOTATE_Eim_out;
            ANNOTATE_Ere_out;
            #85;
        end
    end

    initial begin  // Open the annotations file...
        TX_FILE = $fopen("D:\\xilinx\\lianxi\\diexingbianhuan\\test.ano");
        #1200 // Final time:  1200 ns
        $display("Success! Annotation Simulation Complete.");
        $fdisplay(TX_FILE, "Total[%d]", TX_ERROR);
        $fclose(TX_FILE);
        $finish;
    end

    initial begin
        // -------------  Current Time:  85ns
        #85;
        Aim_in = 8'b00010010;
        Are_in = 8'b00010100;
        Bim_in = 8'b00000100;
        cms_in = 9'b000010000;
        cps_in = 9'b000010000;
        c_in = 8'b00001100;
        // -------------------------------------
        // -------------  Current Time:  285ns
        #200;
        Are_in = 8'b00110100;
        Bim_in = 8'b00000101;
        Bre_in = 8'b00000110;
        // -------------------------------------
        // -------------  Current Time:  485ns
        #200;
        Aim_in = 8'b00010011;
        Are_in = 8'b00111100;
        Bre_in = 8'b00000111;
        cms_in = 9'b000010100;
        cps_in = 9'b000010100;
        // -------------------------------------
        // -------------  Current Time:  685ns
        #200;
        c_in = 8'b00001000;
        // -------------------------------------
    end

    task ANNOTATE_Dim_out;
        #0 begin
            $fdisplay(TX_FILE, "Annotate[%d,Dim_out,%b]", $time, Dim_out);
            $fflush(TX_FILE);
            TX_ERROR = TX_ERROR + 1;
        end
    endtask

    task ANNOTATE_Dre_out;
        #0 begin
            $fdisplay(TX_FILE, "Annotate[%d,Dre_out,%b]", $time, Dre_out);
            $fflush(TX_FILE);
            TX_ERROR = TX_ERROR + 1;
        end
    endtask

    task ANNOTATE_Eim_out;
        #0 begin
            $fdisplay(TX_FILE, "Annotate[%d,Eim_out,%b]", $time, Eim_out);
            $fflush(TX_FILE);
            TX_ERROR = TX_ERROR + 1;
        end
    endtask

    task ANNOTATE_Ere_out;
        #0 begin
            $fdisplay(TX_FILE, "Annotate[%d,Ere_out,%b]", $time, Ere_out);
            $fflush(TX_FILE);
            TX_ERROR = TX_ERROR + 1;
        end
    endtask

endmodule