////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 8.1i
//  \   \         Application : sch2verilog
//  /   /         Filename : lian.vf
// /___/   /\     Timestamp : 11/22/2006 10:17:57
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: D:\xilinx\bin\nt\sch2verilog.exe -intstyle ise -family spartan3 -w D:/xilinx/lianxi/diexingbianhuan/lian.sch lian.vf
//Design Name: lian
//Device: spartan3
//Purpose:
//    This verilog netlist is translated from an ECS schematic.It can be 
//    synthesized and simulated, but it should not be modified. 
//
`timescale 1ns / 1ps

module lian(Aim_in, 
            Are_in, 
            Bim_in, 
            Bre_in, 
            clk, 
            cms_in, 
            cps_in, 
            c_in, 
            Dim_out, 
            Dre_out, 
            Eim_out, 
            Ere_out);

    input [7:0] Aim_in;
    input [7:0] Are_in;
    input [7:0] Bim_in;
    input [7:0] Bre_in;
    input clk;
    input [8:0] cms_in;
    input [8:0] cps_in;
    input [7:0] c_in;
   output [7:0] Dim_out;
   output [7:0] Dre_out;
   output [7:0] Eim_out;
   output [7:0] Ere_out;
   
   wire [7:0] XLXN_2;
   wire [7:0] XLXN_6;
   wire [7:0] XLXN_37;
   wire [7:0] XLXN_42;
   wire [7:0] XLXN_47;
   wire [7:0] XLXN_53;
   wire [8:0] XLXN_69;
   wire [7:0] XLXN_70;
   wire [8:0] XLXN_71;
   wire [7:0] XLXN_72;
   wire XLXN_81;
   
   ccmul XLXI_1 (.clk(clk), 
                 .cms_in(cms_in[8:0]), 
                 .cps_in(cps_in[8:0]), 
                 .c_in(c_in[7:0]), 
                 .x_in(Bre_in[7:0]), 
                 .y_in(Bim_in[7:0]), 
                 .i_out(XLXN_2[7:0]), 
                 .r_out(XLXN_6[7:0]));
   jiajia XLXI_2 (.A(XLXN_37[7:0]), 
                  .B(XLXN_2[7:0]), 
                  .S(XLXN_69[8:0]));
   jianjian XLXI_3 (.A(XLXN_37[7:0]), 
                    .B(XLXN_2[7:0]), 
                    .B_IN(XLXN_81), 
                    .S(XLXN_47[7:0]));
   jianjian XLXI_4 (.A(XLXN_42[7:0]), 
                    .B(XLXN_6[7:0]), 
                    .B_IN(XLXN_81), 
                    .S(XLXN_53[7:0]));
   jiajia XLXI_5 (.A(XLXN_6[7:0]), 
                  .B(XLXN_42[7:0]), 
                  .S(XLXN_71[8:0]));
   dchufa XLXI_15 (.clk(clk), 
                   .data_in(XLXN_70[7:0]), 
                   .data_out(Dim_out[7:0]));
   dchufa XLXI_16 (.clk(clk), 
                   .data_in(Are_in[7:0]), 
                   .data_out(XLXN_42[7:0]));
   dchufa XLXI_17 (.clk(clk), 
                   .data_in(Aim_in[7:0]), 
                   .data_out(XLXN_37[7:0]));
   dchufa XLXI_18 (.clk(clk), 
                   .data_in(XLXN_47[7:0]), 
                   .data_out(Eim_out[7:0]));
   dchufa XLXI_19 (.clk(clk), 
                   .data_in(XLXN_72[7:0]), 
                   .data_out(Dre_out[7:0]));
   dchufa XLXI_20 (.clk(clk), 
                   .data_in(XLXN_53[7:0]), 
                   .data_out(Ere_out[7:0]));
   chuli XLXI_21 (.shu_in(XLXN_69[8:0]), 
                  .shu_out(XLXN_70[7:0]));
   chuli XLXI_22 (.shu_in(XLXN_71[8:0]), 
                  .shu_out(XLXN_72[7:0]));
   yuan XLXI_23 (.yu(XLXN_81));
endmodule