?? hardware.h
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#ifndef _HARDWARE_H
#define _HARDWARE_H
#include "hardware_reg.h"
//***************************************
//PMU module clk
//*************************************
#define CLK_INTC (1 << 14)
#define CLK_PMU (1 << 13)
#define CLK_RTC (1 << 12)
#define CLK_GPT (1 << 11)
#define CLK_SPI (1 << 10)
#define CLK_UART0 (1 << 9)
#define CLK_UART1 (1 << 8)
#define CLK_GPIO (1 << 7)
#define CLK_MMC (1 << 6)
#define CLK_AC97 (1 << 5)
#define CLK_DMA (1 << 4)
#define CLK_MMA (1 << 3)
#define CLK_LCDC (1 << 2)
#define CLK_ESRAM (1 << 1)
#define CLK_EMI (1)
/*************************************
macros for INTC
*************************************/
/*interrupt resources */
#define INT_RTC 31
#define INT_DMA 30
#define INT_EMI 29
#define INT_GPT 28
#define INT_USB 27
#define INT_SPI 26
#define INT_MMC 25
#define INT_UART1 24
#define INT_UART2 23
#define INT_I2C 22
#define INT_AC97 21
#define INT_MMA 20
#define INT_EXT17 19
#define INT_EXT16 18
#define INT_EXT15 17
#define INT_EXT0 15
#define INT_EXT1 1
#define INT_EXT2 13
#define INT_EXT3 12
#define INT_EXT4 11
#define INT_EXT5 10
#define INT_EXT6 9
#define INT_EXT7 8
#define INT_EXT8 7
#define INT_EXT9 6
#define INT_EXT10 5
#define INT_EXT11 4
#define INT_EXT12 3
#define INT_EXT13 2
#define INT_EXT14 14
/*************************************
macros for RTC
*************************************/
#define RTC_CTRL_RTCEN 0XFFFFFFFE //bit0 to be 0 is effective
#define RTC_CTRL_WDOGEN 0X02 //bit1 to be 1 is effective
#define RTC_IEN_SAMON 0X01 //Sample int enable on
#define RTC_IEN_SECON 0X02 //Second roll int enable on
#define RTC_IEN_MINON 0x04 //Minute roll int enable on
#define RTC_IEN_ALMON 0X08 //Alarm int enable on
#define RTC_IEN_WDOGON ~(1 << 4) //Watchdog int enable on
#define RTC_IEN_RESET 0X20 //When watchdog timeout,reset request to reset module enable bit
#define RTC_ISTAS_SAM 0X01
#define RTC_ISTAS_SEC 0X02
#define RTC_ISTAS_MIN 0X04
#define RTC_ISTAS_ALM 0X08
#define RTC_ISTAS_WDOG 0X10
#define RTC_WSVCE_VAL 0xAAAA
/****************************************
macros for GPT
****************************************/
#define GPT1_CNTL_GPTEN 0X01
#define GPT1_CNTL_NOCLK 0X00
#define GPT1_CNTL_SYSCLK (0X01 << 1)
#define GPT1_CNTL_SYSCLK8 (0X02 << 1)
#define GPT1_CNTL_SYSCLK16 (0X03 << 1)
#define GPT1_CNTL_COMIEN 0X10
#define GPT1_CNTL_NOCAP 0X00
#define GPT1_CNTL_CAPUP (0X01 << 6)
#define GPT1_CNTL_CAPDOWN (0X02 << 6)
#define GPT1_CNTL_CAPALL (0X03 << 6)
#define GPT1_CNTL_FREERUN (1 << 8)
#define GPT1_CNTL_PWM (1 << 18)
#define GPT1_CNTL_SWR (1 << 15)
#define GPT1_STAS_CMP 0X01
#define GPT1_STAS_CAP 0X02
/*****************************************
macros for UART
*****************************************/
#define UART1_IER_MODEM 0X01
#define UART1_IER_RLS 0X02
#define UART1_IER_THR 0X04
#define UART1_IER_RDA 0X08
#define UART1_IIR_MODEM 0X00
#define UART1_IIR_THR 0X01
#define UART1_IIR_RDA 0X02
#define UART1_IIR_RLS 0X03
#define UART1_IIR_TMO 0X06
#define UART1_LCR_DIV 0X80
/*****************************************
macros for PWM
*****************************************/
#define PWM1_CNTL_PWM (1 << 18)
#define PWM1_CNTL_DMA (1 << 17)
#define PWM1_CNTL_RST (1 << 16)
#define PWM1_CNTL_CLK32 (1 << 15)
#define PWM1_CNTL_IEN (1 << 13)
#define PWM1_CNTL_WOK (1 << 12)
#define PWM1_CNTL_PWMEN (1 << 11)
#define PWM1_CNTL_NOREP 0X00
#define PWM1_CNTL_REP2 (0X01 << 9)
#define PWM1_CNTL_REP3 (0X10 << 9)
#define PWM1_CNTL_REP7 (0X11 << 9)
#define PWM1_CNTL_32K 0X00
#define PWM1_CNTL_16K 0X01
#define PWM1_CNTL_8K 0X10
#define PWM1_CNTL_4K 0X11
/*****************************************
macros for EMI
*****************************************/
#define EMIADDR_CSGBAB_val 0x24002000 //base adress of csa:0x20000000
//base adress of csb:0x24000000(none now)
#define EMIADDR_CSGBCD_val 0x2c002800 //base adress of csc:0x28000000
//base adress of csc:0x2C000000(none now)
#define EMIADDR_CSGBEF_val 0x34003000 //base adress of csc:0x30000000
//base adress of csc:0x34000000
#define EMIADDR_SMCONF_val 0x9b010333 //write cycle: 3 read cycle:3
//csa:32_bit sram
//csb:none
//csc:32_bit sram
//csd:none
//cde:16_bit sdram
//cdf:32 bit sdram
#define EMIADDR_SDCONF1_val 0x0110a077 //12 row * 9 column
//non_Interleaved Address Mode
//2 row every flesh clock edge
//hang_up after 64 clocks after last access
//CAS = 2 clock
//3 clock between precharge and active command
//4 clock between active and write/read command toward the same bank
//7 clock between refresh command and later commands
#define EMIADDR_SDCONF2_val 0x80001860 //Initialize sdam;
//refresh cyccle:64*0x186 clocks
//refresh all rows once a time
#define EMIADDR_NANDCONF_VAL 0x02200aaa //4 address 0x1aa3aa
//Trr 10 cycles
//Tclh 2 cycles
//Talh 2 cycles
//Twh 3 cycles
//Read_width 10 cycles
//Writ_width 10 cycles
/*****************************************
macros for MMC
*****************************************/
#define SD 0
#define MMC 1
#define CARD 1
#define MMC_GO_IDLE_STATE 0 // bc
#define MMC_SEND_OP_COND 1 // bcr [31:0] OCR R3
#define MMC_ALL_SEND_CID 2 // bcr R2
#define MMC_SET_RELATIVE_ADDR 3 // ac [31:16] RCA R1
#define MMC_SET_DSR 4 // bc [31:16] RCA
#define MMC_SET_BUS_WIDTH 6 //
#define MMC_SELECT_CARD 7 // ac [31:16] RCA R1
#define MMC_SEND_CSD 9 // ac [31:16] RCA R2
#define MMC_SEND_CID 10 // ac [31:16] RCA R2
#define MMC_READ_DAT_UNTIL_STOP 11 // adtc [31:0] dadr R1
#define MMC_STOP_TRANSMISSION 12 // ac R1b
#define MMC_SEND_STATUS 13 // ac [31:16] RCA R1
#define MMC_GO_INACTIVE_STATE 15 // ac [31:16] RCA
/* class 2 */
#define MMC_SET_BLOCKLEN 16 // ac [31:0] block len R1
#define MMC_READ_SINGLE_BLOCK 17 // adtc [31:0] data addr R1
#define MMC_READ_MULTIPLE_BLOCK 18 // adtc [31:0] data addr R1
// class 3 */
#define MMC_WRITE_DAT_UNTIL_STOP 20 // adtc [31:0] data addr R1
// class 4 */
#define MMC_SET_BLOCK_COUNT 23 // adtc [31:0] data addr R1
#define MMC_WRITE_BLOCK 24 // adtc [31:0] data addr R1
#define MMC_WRITE_MULTIPLE_BLOCK 25 // adtc R1
#define MMC_PROGRAM_CID 26 // adtc R1
#define MMC_PROGRAM_CSD 27 // adtc R1
// class 5 */
#define MMC_ERASE_SECTOR_START 32
#define MMC_ERASE_SECTOR_END 33
#define MMC_UNTAG_SECTOR 34
#define MMC_ERASE_GROUP_START 35 // ac [31:0] data addr R1
#define MMC_ERASE_GROUP_END 36 ///ac [31:0] data addr R1
#define MMC_UNTAG_GROUP 37
#define MMC_ERASE 38 // ac R1b
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