/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h,v 1.43 2003/11/06 18:38:00 tsi Exp $ *//* * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and *                VA Linux Systems Inc., Fremont, California. * * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation on the rights to use, copy, modify, merge, * publish, distribute, sublicense, and/or sell copies of the Software, * and to permit persons to whom the Software is furnished to do so, * subject to the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial * portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. *//* * Authors: *   Kevin E. Martin <martin@xfree86.org> *   Rickard E. Faith <faith@valinux.com> *   Alan Hourihane <alanh@fairlite.demon.co.uk> * */#ifndef _RADEON_H_#define _RADEON_H_#include <stdlib.h>		/* For abs() */#include <unistd.h>		/* For usleep() */#include "xf86str.h"#include "compiler.h"#include "xf86fbman.h"				/* PCI support */#include "xf86Pci.h"#ifdef USE_EXA#include "exa.h"#endif#ifdef USE_XAA#include "xaa.h"#endif				/* Exa and Cursor Support */#include "vbe.h"#include "xf86Cursor.h"				/* DDC support */#include "xf86DDC.h"				/* Xv support */#include "xf86xv.h"#include "radeon_probe.h"				/* DRI support */#ifdef XF86DRI#define _XF86DRI_SERVER_#include "radeon_dripriv.h"#include "dri.h"#include "GL/glxint.h"#endif				/* Render support */#ifdef RENDER#include "picturestr.h"#endiftypedef enum {    OPTION_NOACCEL,    OPTION_SW_CURSOR,    OPTION_DAC_6BIT,    OPTION_DAC_8BIT,#ifdef XF86DRI    OPTION_BUS_TYPE,    OPTION_CP_PIO,    OPTION_USEC_TIMEOUT,    OPTION_AGP_MODE,    OPTION_AGP_FW,    OPTION_GART_SIZE,    OPTION_GART_SIZE_OLD,    OPTION_RING_SIZE,    OPTION_BUFFER_SIZE,    OPTION_DEPTH_MOVE,    OPTION_PAGE_FLIP,    OPTION_NO_BACKBUFFER,    OPTION_XV_DMA,    OPTION_FBTEX_PERCENT,    OPTION_DEPTH_BITS,#ifdef USE_EXA    OPTION_ACCEL_DFS,#endif#endif    OPTION_PANEL_OFF,    OPTION_DDC_MODE,    OPTION_MONITOR_LAYOUT,    OPTION_IGNORE_EDID,    OPTION_FBDEV,    OPTION_MERGEDFB,    OPTION_CRT2HSYNC,    OPTION_CRT2VREFRESH,    OPTION_CRT2POS,    OPTION_METAMODES,    OPTION_MERGEDDPI,    OPTION_RADEONXINERAMA,    OPTION_CRT2ISSCRN0,    OPTION_MERGEDFBNONRECT,    OPTION_MERGEDFBMOUSER,    OPTION_DISP_PRIORITY,    OPTION_PANEL_SIZE,    OPTION_MIN_DOTCLOCK,    OPTION_COLOR_TILING,#ifdef XvExtension    OPTION_VIDEO_KEY,    OPTION_RAGE_THEATRE_CRYSTAL,    OPTION_RAGE_THEATRE_TUNER_PORT,    OPTION_RAGE_THEATRE_COMPOSITE_PORT,    OPTION_RAGE_THEATRE_SVIDEO_PORT,    OPTION_TUNER_TYPE,    OPTION_RAGE_THEATRE_MICROC_PATH,    OPTION_RAGE_THEATRE_MICROC_TYPE,#endif#ifdef RENDER    OPTION_RENDER_ACCEL,    OPTION_SUBPIXEL_ORDER,#endif    OPTION_SHOWCACHE,    OPTION_DYNAMIC_CLOCKS,    OPTION_BIOS_HOTKEYS,    OPTION_VGA_ACCESS,    OPTION_REVERSE_DDC,    OPTION_LVDS_PROBE_PLL,    OPTION_ACCELMETHOD,    OPTION_CONSTANTDPI} RADEONOpts;/* ------- mergedfb support ------------- */		/* Psuedo Xinerama support */#define NEED_REPLIES  		/* ? */#define EXTENSION_PROC_ARGS void *#include "extnsionst.h"  	/* required */#include <X11/extensions/panoramiXproto.h>  	/* required */#define RADEON_XINERAMA_MAJOR_VERSION  1#define RADEON_XINERAMA_MINOR_VERSION  1/* Relative merge position */typedef enum {   radeonLeftOf,   radeonRightOf,   radeonAbove,   radeonBelow,   radeonClone} RADEONScrn2Rel;typedef struct _region {    int x0,x1,y0,y1;} region;/* ------------------------------------- */#define RADEON_DEBUG            1 /* Turn off debugging output               */#define RADEON_IDLE_RETRY      16 /* Fall out of idle loops after this count */#define RADEON_TIMEOUT    2000000 /* Fall out of wait loops after this count *//* Buffer are aligned on 4096 byte boundaries */#define RADEON_BUFFER_ALIGN 0x00000fff#define RADEON_VBIOS_SIZE 0x00010000#define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX				   * Need to comfirm this is not used				   * for something else.				   */#if RADEON_DEBUG#define RADEONTRACE(x)						\do {									\    ErrorF("(**) %s(%d): ", RADEON_NAME, pScrn->scrnIndex);		\    ErrorF x;								\} while(0)#else#define RADEONTRACE(x) do { } while(0)#endif/* Other macros */#define RADEON_ARRAY_SIZE(x)  (sizeof(x)/sizeof(x[0]))#define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1))#define RADEONPTR(pScrn)      ((RADEONInfoPtr)(pScrn)->driverPrivate)typedef struct {				/* Common registers */    CARD32            ovr_clr;    CARD32            ovr_wid_left_right;    CARD32            ovr_wid_top_bottom;    CARD32            ov0_scale_cntl;    CARD32            mpp_tb_config;    CARD32            mpp_gp_config;    CARD32            subpic_cntl;    CARD32            viph_control;    CARD32            i2c_cntl_1;    CARD32            gen_int_cntl;    CARD32            cap0_trig_cntl;    CARD32            cap1_trig_cntl;    CARD32            bus_cntl;    CARD32            bios_4_scratch;    CARD32            bios_5_scratch;    CARD32            bios_6_scratch;    CARD32            surface_cntl;    CARD32            surfaces[8][3];    CARD32            mc_agp_location;    CARD32            mc_fb_location;    CARD32            display_base_addr;    CARD32            display2_base_addr;    CARD32            ov0_base_addr;				/* Other registers to save for VT switches */    CARD32            dp_datatype;    CARD32            rbbm_soft_reset;    CARD32            clock_cntl_index;    CARD32            amcgpio_en_reg;    CARD32            amcgpio_mask;				/* CRTC registers */    CARD32            crtc_gen_cntl;    CARD32            crtc_ext_cntl;    CARD32            dac_cntl;    CARD32            crtc_h_total_disp;    CARD32            crtc_h_sync_strt_wid;    CARD32            crtc_v_total_disp;    CARD32            crtc_v_sync_strt_wid;    CARD32            crtc_offset;    CARD32            crtc_offset_cntl;    CARD32            crtc_pitch;    CARD32            disp_merge_cntl;    CARD32            grph_buffer_cntl;    CARD32            crtc_more_cntl;				/* CRTC2 registers */    CARD32            crtc2_gen_cntl;    CARD32            dac2_cntl;    CARD32            disp_output_cntl;    CARD32            disp_hw_debug;    CARD32            disp2_merge_cntl;    CARD32            grph2_buffer_cntl;    CARD32            crtc2_h_total_disp;    CARD32            crtc2_h_sync_strt_wid;    CARD32            crtc2_v_total_disp;    CARD32            crtc2_v_sync_strt_wid;    CARD32            crtc2_offset;    CARD32            crtc2_offset_cntl;    CARD32            crtc2_pitch;				/* Flat panel registers */    CARD32            fp_crtc_h_total_disp;    CARD32            fp_crtc_v_total_disp;    CARD32            fp_gen_cntl;    CARD32            fp2_gen_cntl;    CARD32            fp_h_sync_strt_wid;    CARD32            fp2_h_sync_strt_wid;    CARD32            fp_horz_stretch;    CARD32            fp_panel_cntl;    CARD32            fp_v_sync_strt_wid;    CARD32            fp2_v_sync_strt_wid;    CARD32            fp_vert_stretch;    CARD32            lvds_gen_cntl;    CARD32            lvds_pll_cntl;    CARD32            tmds_pll_cntl;    CARD32            tmds_transmitter_cntl;				/* Computed values for PLL */    CARD32            dot_clock_freq;    CARD32            pll_output_freq;    int               feedback_div;    int               post_div;				/* PLL registers */    unsigned          ppll_ref_div;    unsigned          ppll_div_3;    CARD32            htotal_cntl;				/* Computed values for PLL2 */    CARD32            dot_clock_freq_2;    CARD32            pll_output_freq_2;    int               feedback_div_2;    int               post_div_2;				/* PLL2 registers */    CARD32            p2pll_ref_div;    CARD32            p2pll_div_0;    CARD32            htotal_cntl2;				/* Pallet */    Bool              palette_valid;    CARD32            palette[256];    CARD32            palette2[256];    CARD32            tv_dac_cntl;} RADEONSaveRec, *RADEONSavePtr;typedef struct {    CARD16            reference_freq;    CARD16            reference_div;    CARD32            min_pll_freq;    CARD32            max_pll_freq;    CARD16            xclk;} RADEONPLLRec, *RADEONPLLPtr;typedef struct {    int               bitsPerPixel;    int               depth;    int               displayWidth;    int               displayHeight;    int               pixel_code;    int               pixel_bytes;    DisplayModePtr    mode;} RADEONFBLayout;typedef enum {    CHIP_FAMILY_UNKNOW,    CHIP_FAMILY_LEGACY,    CHIP_FAMILY_RADEON,    CHIP_FAMILY_RV100,    CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/    CHIP_FAMILY_RV200,    CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */    CHIP_FAMILY_R200,    CHIP_FAMILY_RV250,    CHIP_FAMILY_RS300,    /* RS300/RS350 */    CHIP_FAMILY_RV280,    CHIP_FAMILY_R300,    CHIP_FAMILY_R350,    CHIP_FAMILY_RV350,    CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */    CHIP_FAMILY_R420,     /* R420/R423/M18 */    CHIP_FAMILY_RV410,    /* RV410, M26 */    CHIP_FAMILY_RS400,    /* xpress 200, 200m (RS400/410/480) */    CHIP_FAMILY_LAST} RADEONChipFamily;#define IS_RV100_VARIANT ((info->ChipFamily == CHIP_FAMILY_RV100)  ||  \        (info->ChipFamily == CHIP_FAMILY_RV200)  ||  \        (info->ChipFamily == CHIP_FAMILY_RS100)  ||  \        (info->ChipFamily == CHIP_FAMILY_RS200)  ||  \        (info->ChipFamily == CHIP_FAMILY_RV250)  ||  \        (info->ChipFamily == CHIP_FAMILY_RV280)  ||  \        (info->ChipFamily == CHIP_FAMILY_RS300))#define IS_R300_VARIANT ((info->ChipFamily == CHIP_FAMILY_R300)  ||  \        (info->ChipFamily == CHIP_FAMILY_RV350) ||  \        (info->ChipFamily == CHIP_FAMILY_R350)  ||  \        (info->ChipFamily == CHIP_FAMILY_RV380) ||  \        (info->ChipFamily == CHIP_FAMILY_R420)  ||  \        (info->ChipFamily == CHIP_FAMILY_RV410) ||  \        (info->ChipFamily == CHIP_FAMILY_RS400))