pll->min_pll_freq,	       pll->max_pll_freq,	       pll->xclk);    return TRUE;}/* This is called by R128PreInit to set up the default visual. */static Bool R128PreInitVisual(ScrnInfoPtr pScrn){    R128InfoPtr info          = R128PTR(pScrn);    if (!xf86SetDepthBpp(pScrn, 0, 0, 0, (Support24bppFb					  | Support32bppFb					  | SupportConvert32to24					  )))	return FALSE;    switch (pScrn->depth) {    case 8:    case 15:    case 16:    case 24:	break;    default:	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,		   "Given depth (%d) is not supported by %s driver\n",		   pScrn->depth, R128_DRIVER_NAME);	return FALSE;    }    xf86PrintDepthBpp(pScrn);    info->fifo_slots  = 0;    info->pix24bpp    = xf86GetBppFromDepth(pScrn, pScrn->depth);    info->CurrentLayout.bitsPerPixel = pScrn->bitsPerPixel;    info->CurrentLayout.depth        = pScrn->depth;    info->CurrentLayout.pixel_bytes  = pScrn->bitsPerPixel / 8;    info->CurrentLayout.pixel_code   = (pScrn->bitsPerPixel != 16				       ? pScrn->bitsPerPixel				       : pScrn->depth);    xf86DrvMsg(pScrn->scrnIndex, X_INFO,	       "Pixel depth = %d bits stored in %d byte%s (%d bpp pixmaps)\n",	       pScrn->depth,	       info->CurrentLayout.pixel_bytes,	       info->CurrentLayout.pixel_bytes > 1 ? "s" : "",	       info->pix24bpp);    if (!xf86SetDefaultVisual(pScrn, -1)) return FALSE;    if (pScrn->depth > 8 && pScrn->defaultVisual != TrueColor) {	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,		   "Default visual (%s) is not supported at depth %d\n",		   xf86GetVisualName(pScrn->defaultVisual), pScrn->depth);	return FALSE;    }    return TRUE;}/* This is called by R128PreInit to handle all color weight issues. */static Bool R128PreInitWeight(ScrnInfoPtr pScrn){    R128InfoPtr info          = R128PTR(pScrn);				/* Save flag for 6 bit DAC to use for				   setting CRTC registers.  Otherwise use				   an 8 bit DAC, even if xf86SetWeight sets				   pScrn->rgbBits to some value other than				   8. */    info->dac6bits = FALSE;    if (pScrn->depth > 8) {	rgb defaultWeight = { 0, 0, 0 };	if (!xf86SetWeight(pScrn, defaultWeight, defaultWeight)) return FALSE;    } else {	pScrn->rgbBits = 8;	if (xf86ReturnOptValBool(info->Options, OPTION_DAC_6BIT, FALSE)) {	    pScrn->rgbBits = 6;	    info->dac6bits = TRUE;	}    }    xf86DrvMsg(pScrn->scrnIndex, X_INFO,	       "Using %d bits per RGB (%d bit DAC)\n",	       pScrn->rgbBits, info->dac6bits ? 6 : 8);    return TRUE;}/* This is called by R128PreInit to handle config file overrides for things   like chipset and memory regions.  Also determine memory size and type.   If memory type ever needs an override, put it in this routine. */static Bool R128PreInitConfig(ScrnInfoPtr pScrn){    R128InfoPtr   info      = R128PTR(pScrn);    unsigned char *R128MMIO = info->MMIO;    EntityInfoPtr pEnt      = info->pEnt;    GDevPtr       dev       = pEnt->device;    int           offset    = 0;        /* RAM Type */    MessageType   from;				/* Chipset */    from = X_PROBED;    if (dev->chipset && *dev->chipset) {	info->Chipset  = xf86StringToToken(R128Chipsets, dev->chipset);	from           = X_CONFIG;    } else if (dev->chipID >= 0) {	info->Chipset  = dev->chipID;	from           = X_CONFIG;    } else {	info->Chipset = info->PciInfo->chipType;    }    pScrn->chipset = (char *)xf86TokenToString(R128Chipsets, info->Chipset);    if (!pScrn->chipset) {	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,		   "ChipID 0x%04x is not recognized\n", info->Chipset);	return FALSE;    }    if (info->Chipset < 0) {	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,		   "Chipset \"%s\" is not recognized\n", pScrn->chipset);	return FALSE;    }    xf86DrvMsg(pScrn->scrnIndex, from,	       "Chipset: \"%s\" (ChipID = 0x%04x)\n",	       pScrn->chipset,	       info->Chipset);				/* Framebuffer */    from             = X_PROBED;    info->LinearAddr = info->PciInfo->memBase[0] & 0xfc000000;    pScrn->memPhysBase = info->LinearAddr;    if (dev->MemBase) {	xf86DrvMsg(pScrn->scrnIndex, X_INFO,		   "Linear address override, using 0x%08lx instead of 0x%08lx\n",		   dev->MemBase,		   info->LinearAddr);	info->LinearAddr = dev->MemBase;	from             = X_CONFIG;    } else if (!info->LinearAddr) {	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,		   "No valid linear framebuffer address\n");	return FALSE;    }    xf86DrvMsg(pScrn->scrnIndex, from,	       "Linear framebuffer at 0x%08lx\n", info->LinearAddr);				/* MMIO registers */    from             = X_PROBED;    info->MMIOAddr   = info->PciInfo->memBase[2] & 0xffffff00;    if (dev->IOBase) {	xf86DrvMsg(pScrn->scrnIndex, X_INFO,		   "MMIO address override, using 0x%08lx instead of 0x%08lx\n",		   dev->IOBase,		   info->MMIOAddr);	info->MMIOAddr = dev->IOBase;	from           = X_CONFIG;    } else if (!info->MMIOAddr) {	xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid MMIO address\n");	return FALSE;    }    xf86DrvMsg(pScrn->scrnIndex, from,	       "MMIO registers at 0x%08lx\n", info->MMIOAddr);				/* BIOS */    from              = X_PROBED;    info->BIOSAddr    = info->PciInfo->biosBase & 0xfffe0000;    if (dev->BiosBase) {	xf86DrvMsg(pScrn->scrnIndex, X_INFO,		   "BIOS address override, using 0x%08lx instead of 0x%08lx\n",		   dev->BiosBase,		   info->BIOSAddr);	info->BIOSAddr = dev->BiosBase;	from           = X_CONFIG;    }    if (info->BIOSAddr) {	xf86DrvMsg(pScrn->scrnIndex, from,		   "BIOS at 0x%08lx\n", info->BIOSAddr);    }				/* Flat panel (part 1) */    if (xf86GetOptValBool(info->Options, OPTION_PROG_FP_REGS,			  &info->HasPanelRegs)) {	xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,		   "Turned flat panel register programming %s\n",		   info->HasPanelRegs ? "on" : "off");	xf86DrvMsg(pScrn->scrnIndex, X_WARNING,		   "\n\nWARNING: Forcing the driver to use/not use the flat panel registers\nmight damage your flat panel.  Use at your *OWN* *RISK*.\n\n");    } else {        info->isDFP = FALSE;        info->isPro2 = FALSE;        info->HasCRTC2 = FALSE;	switch (info->Chipset) {	/* R128 Pro and Pro2 can have DFP, we will deal with it.	   No support for dual-head/xinerama yet.           M3 can also have DFP, no support for now */	case PCI_CHIP_RAGE128TF:	case PCI_CHIP_RAGE128TL:	case PCI_CHIP_RAGE128TR:	/* FIXME: RAGE128 TS/TT/TU are assumed to be PRO2 as all 6 chips came	 *        out at the same time, so are of the same family likely.	 *        This requires confirmation however to be fully correct.	 *        Mike A. Harris <mharris@redhat.com>	 */	case PCI_CHIP_RAGE128TS:	case PCI_CHIP_RAGE128TT:	case PCI_CHIP_RAGE128TU: info->isPro2 = TRUE;	/* FIXME: RAGE128 P[ABCEGHIJKLMNOQSTUVWX] are assumed to have DFP	 *        capability, as the comment at the top suggests.	 *        This requires confirmation however to be fully correct.	 *        Mike A. Harris <mharris@redhat.com>	 */	case PCI_CHIP_RAGE128PA:	case PCI_CHIP_RAGE128PB:	case PCI_CHIP_RAGE128PC:	case PCI_CHIP_RAGE128PE:	case PCI_CHIP_RAGE128PG:	case PCI_CHIP_RAGE128PH:	case PCI_CHIP_RAGE128PI:	case PCI_CHIP_RAGE128PJ:	case PCI_CHIP_RAGE128PK:	case PCI_CHIP_RAGE128PL:	case PCI_CHIP_RAGE128PM:	case PCI_CHIP_RAGE128PN:	case PCI_CHIP_RAGE128PO:	case PCI_CHIP_RAGE128PQ:	case PCI_CHIP_RAGE128PS:	case PCI_CHIP_RAGE128PT:	case PCI_CHIP_RAGE128PU:	case PCI_CHIP_RAGE128PV:	case PCI_CHIP_RAGE128PW:	case PCI_CHIP_RAGE128PX:	case PCI_CHIP_RAGE128PD:	case PCI_CHIP_RAGE128PF:	case PCI_CHIP_RAGE128PP:	case PCI_CHIP_RAGE128PR: info->isDFP = TRUE; break;	case PCI_CHIP_RAGE128LE:	case PCI_CHIP_RAGE128LF:	case PCI_CHIP_RAGE128MF:	case PCI_CHIP_RAGE128ML: 			info->HasPanelRegs = TRUE;  			/* which chips support dualhead? */			info->HasCRTC2 = TRUE;  			break;	case PCI_CHIP_RAGE128RE:	case PCI_CHIP_RAGE128RF:	case PCI_CHIP_RAGE128RG:	case PCI_CHIP_RAGE128RK:	case PCI_CHIP_RAGE128RL:	case PCI_CHIP_RAGE128SM:	/* FIXME: RAGE128 S[EFGHKLN] are assumed to be like the SM above as	 *        all of them are listed as "Rage 128 4x" in ATI docs.	 *        This requires confirmation however to be fully correct.	 *        Mike A. Harris <mharris@redhat.com>	 */	case PCI_CHIP_RAGE128SE:	case PCI_CHIP_RAGE128SF:	case PCI_CHIP_RAGE128SG:	case PCI_CHIP_RAGE128SH:	case PCI_CHIP_RAGE128SK:	case PCI_CHIP_RAGE128SL:	case PCI_CHIP_RAGE128SN:	default:                 info->HasPanelRegs = FALSE; break;	}    }				/* Read registers used to determine options */    from                      = X_PROBED;    R128MapMMIO(pScrn);    R128MMIO                  = info->MMIO;    if (info->FBDev)	pScrn->videoRam       = fbdevHWGetVidmem(pScrn) / 1024;    else	pScrn->videoRam       = INREG(R128_CONFIG_MEMSIZE) / 1024;    info->MemCntl             = INREG(R128_MEM_CNTL);    info->BusCntl             = INREG(R128_BUS_CNTL);    /* On non-flat panel systems, the default is to display to the CRT,       and on flat panel systems, the default is to display to the flat       panel unless the user explicity chooses otherwise using the "Display"       config file setting.  BIOS_5_SCRATCH holds the display device on flat       panel systems only. */    if (info->HasPanelRegs) {        char *Display = xf86GetOptValString(info->Options, OPTION_DISPLAY);	if (info->FBDev)	    xf86DrvMsg(pScrn->scrnIndex, X_INFO,		     "Option \"Display\" ignored "		     "(framebuffer device determines display type)\n");	else if (info->IsPrimary || info->IsSecondary)	    info->BIOSDisplay = R128_DUALHEAD;	else if (!Display || !xf86NameCmp(Display, "FP"))	    info->BIOSDisplay = R128_BIOS_DISPLAY_FP;	else if (!xf86NameCmp(Display, "BIOS"))	    info->BIOSDisplay = INREG8(R128_BIOS_5_SCRATCH);	else if (!xf86NameCmp(Display, "Mirror"))	    info->BIOSDisplay = R128_BIOS_DISPLAY_FP_CRT;	else if (!xf86NameCmp(Display, "CRT"))	    info->BIOSDisplay = R128_BIOS_DISPLAY_CRT;	else {	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,		"Unsupported type \"%s\" specified for Option \"Display\".\n"		"\tSupported types are: "		"\"BIOS\", \"Mirror\", \"CRT\" and \"FP\"\n", Display);	    return FALSE;	}    } else {	info->BIOSDisplay     = R128_BIOS_DISPLAY_CRT;    }    R128MMIO                  = NULL;    R128UnmapMMIO(pScrn);				/* RAM */    switch (info->MemCntl & 0x3) {    case 0:                     /* SDR SGRAM 1:1 */	switch (info->Chipset) {	case PCI_CHIP_RAGE128TF:	case PCI_CHIP_RAGE128TL:	case PCI_CHIP_RAGE128TR:	case PCI_CHIP_RAGE128LE:	case PCI_CHIP_RAGE128LF:	case PCI_CHIP_RAGE128MF:	case PCI_CHIP_RAGE128ML:	case PCI_CHIP_RAGE128RE:	case PCI_CHIP_RAGE128RF:	case PCI_CHIP_RAGE128RG: offset = 0; break; /* 128-bit SDR SGRAM 1:1 */	case PCI_CHIP_RAGE128RK:	case PCI_CHIP_RAGE128RL:	case PCI_CHIP_RAGE128SM:	default:                 offset = 1; break; /*  64-bit SDR SGRAM 1:1 */	}	break;    case 1:                      offset = 2; break; /*  64-bit SDR SGRAM 2:1 */    case 2:                      offset = 3; break; /*  64-bit DDR SGRAM     */    default:                     offset = 1; break; /*  64-bit SDR SGRAM 1:1 */    }    info->ram = &R128RAM[offset];    if (dev->videoRam) {	xf86DrvMsg(pScrn->scrnIndex, X_INFO,		   "Video RAM override, using %d kB instead of %d kB\n",		   dev->videoRam,		   pScrn->videoRam);	from             = X_CONFIG;	pScrn->videoRam  = dev->videoRam;    }    xf86DrvMsg(pScrn->scrnIndex, from,	       "VideoRAM: %d kByte (%s)\n", pScrn->videoRam, info->ram->name);    if (info->IsPrimary) {        pScrn->videoRam /= 2;	xf86DrvMsg(pScrn->scrnIndex, X_INFO, 		"Using %dk of videoram for primary head\n",		pScrn->videoRam);    }    if (info->IsSecondary) {          pScrn->videoRam /= 2;        info->LinearAddr += pScrn->videoRam * 1024;	xf86DrvMsg(pScrn->scrnIndex, X_INFO, 		"Using %dk of videoram for secondary head\n",		pScrn->videoRam);    }    pScrn->videoRam  &= ~1023;    info->FbMapSize  = pScrn->videoRam * 1024;				/* Flat panel (part 2) */	switch (info->BIOSDisplay) {	case R128_DUALHEAD:	    xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,		       "Dual display\n");	    break;	case R128_BIOS_DISPLAY_FP:	    xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,		       "Using flat panel for display\n");	    break;	case R128_BIOS_DISPLAY_CRT:	    xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,		       "Using external CRT for display\n");	    break;	case R128_BIOS_DISPLAY_FP_CRT:	    xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,		       "Using both flat panel and external CRT "		       "for display\n");	    break;	}    if (info->HasPanelRegs) {				/* Panel width/height overrides */	info->PanelXRes = 0;	info->PanelYRes = 0;	if (xf86GetOptValInteger(info->Options,				 OPTION_PANEL_WIDTH, &(info->PanelXRes))) {	    xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,		       "Flat panel width: %d\n", info->PanelXRes);	}	if (xf86GetOptValInteger(info->Options,				 OPTION_PANEL_HEIGHT, &(info->PanelYRes))) {	    xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,		       "Flat panel height: %d\n", info->PanelYRes);	}    }#ifdef XF86DRI				/* DMA for Xv */    info->DMAForXv = xf86ReturnOptValBool(info->Options, OPTION_XV_DMA, FALSE);    if (info->DMAForXv) {	xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,		   "Will try to use DMA for Xv image transfers\n");    }				/* AGP/PCI */    if (xf86ReturnOptValBool(info->Options, OPTION_IS_PCI, FALSE)) {	info->IsPCI = TRUE;	xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI-only mode\n");    } else {	switch (info->Chipset) {	case PCI_CHIP_RAGE128LE:	case PCI_CHIP_RAGE128RE:	case PCI_CHIP_RAGE128RK:	case PCI_CHIP_RAGE128PD:	case PCI_CHIP_RAGE128PR:	case PCI_CHIP_RAGE128PP: info->IsPCI = TRUE;  break;	case PCI_CHIP_RAGE128LF:	case PCI_CHIP_RAGE128MF:	case PCI_CHIP_RAGE128ML:	case PCI_CHIP_RAGE128PF:	case PCI_CHIP_RAGE128RF:	case PCI_CHIP_RAGE128RG:	case PCI_CHIP_RAGE128RL: