?? radeon_reg.h
字號:
# define RADEON_HORZ_STRETCH_PIXREP (0 << 25)# define RADEON_HORZ_STRETCH_BLEND (1 << 26)# define RADEON_HORZ_STRETCH_ENABLE (1 << 25)# define RADEON_HORZ_AUTO_RATIO (1 << 27)# define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28)# define RADEON_HORZ_AUTO_RATIO_INC (1 << 31)#define RADEON_FP_V_SYNC_STRT_WID 0x02c8#define RADEON_FP_VERT_STRETCH 0x0290#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8#define RADEON_FP_VERT2_STRETCH 0x0390# define RADEON_VERT_PANEL_SIZE (0xfff << 12)# define RADEON_VERT_PANEL_SHIFT 12# define RADEON_VERT_STRETCH_RATIO_MASK 0xfff# define RADEON_VERT_STRETCH_RATIO_SHIFT 0# define RADEON_VERT_STRETCH_RATIO_MAX 4096# define RADEON_VERT_STRETCH_ENABLE (1 << 25)# define RADEON_VERT_STRETCH_LINEREP (0 << 26)# define RADEON_VERT_STRETCH_BLEND (1 << 26)# define RADEON_VERT_AUTO_RATIO_EN (1 << 27)# define RADEON_VERT_STRETCH_RESERVED 0xf1000000#define RADEON_GEN_INT_CNTL 0x0040#define RADEON_GEN_INT_STATUS 0x0044# define RADEON_VSYNC_INT_AK (1 << 2)# define RADEON_VSYNC_INT (1 << 2)# define RADEON_VSYNC2_INT_AK (1 << 6)# define RADEON_VSYNC2_INT (1 << 6)#define RADEON_GENENB 0x03c3 /* VGA */#define RADEON_GENFC_RD 0x03ca /* VGA */#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */#define RADEON_GENMO_RD 0x03cc /* VGA */#define RADEON_GENMO_WT 0x03c2 /* VGA */#define RADEON_GENS0 0x03c2 /* VGA */#define RADEON_GENS1 0x03da /* VGA, 0x03ba */#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */#define RADEON_GPIO_MONIDB 0x006c#define RADEON_GPIO_CRT2_DDC 0x006c#define RADEON_GPIO_DVI_DDC 0x0064#define RADEON_GPIO_VGA_DDC 0x0060# define RADEON_GPIO_A_0 (1 << 0)# define RADEON_GPIO_A_1 (1 << 1)# define RADEON_GPIO_Y_0 (1 << 8)# define RADEON_GPIO_Y_1 (1 << 9)# define RADEON_GPIO_Y_SHIFT_0 8# define RADEON_GPIO_Y_SHIFT_1 9# define RADEON_GPIO_EN_0 (1 << 16)# define RADEON_GPIO_EN_1 (1 << 17)# define RADEON_GPIO_MASK_0 (1 << 24) /*??*/# define RADEON_GPIO_MASK_1 (1 << 25) /*??*/#define RADEON_GRPH8_DATA 0x03cf /* VGA */#define RADEON_GRPH8_IDX 0x03ce /* VGA */#define RADEON_GUI_SCRATCH_REG0 0x15e0#define RADEON_GUI_SCRATCH_REG1 0x15e4#define RADEON_GUI_SCRATCH_REG2 0x15e8#define RADEON_GUI_SCRATCH_REG3 0x15ec#define RADEON_GUI_SCRATCH_REG4 0x15f0#define RADEON_GUI_SCRATCH_REG5 0x15f4#define RADEON_HEADER 0x0f0e /* PCI */#define RADEON_HOST_DATA0 0x17c0#define RADEON_HOST_DATA1 0x17c4#define RADEON_HOST_DATA2 0x17c8#define RADEON_HOST_DATA3 0x17cc#define RADEON_HOST_DATA4 0x17d0#define RADEON_HOST_DATA5 0x17d4#define RADEON_HOST_DATA6 0x17d8#define RADEON_HOST_DATA7 0x17dc#define RADEON_HOST_DATA_LAST 0x17e0#define RADEON_HOST_PATH_CNTL 0x0130# define RADEON_HDP_SOFT_RESET (1 << 26)# define RADEON_HDP_APER_CNTL (1 << 23)#define RADEON_HTOTAL_CNTL 0x0009 /* PLL */#define RADEON_HTOTAL2_CNTL 0x002e /* PLL */ /* Multimedia I2C bus */#define RADEON_I2C_CNTL_0 0x0090#define RADEON_I2C_CNTL_1 0x0094#define RADEON_I2C_DATA 0x0098#define RADEON_DVI_I2C_CNTL_0 0x02e0#define RADEON_DVI_I2C_CNTL_1 0x02e4 /* ? */#define RADEON_DVI_I2C_DATA 0x02e8#define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */#define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */#define RADEON_IO_BASE 0x0f14 /* PCI */#define RADEON_LATENCY 0x0f0d /* PCI */#define RADEON_LEAD_BRES_DEC 0x1608#define RADEON_LEAD_BRES_LNTH 0x161c#define RADEON_LEAD_BRES_LNTH_SUB 0x1624#define RADEON_LVDS_GEN_CNTL 0x02d0# define RADEON_LVDS_ON (1 << 0)# define RADEON_LVDS_DISPLAY_DIS (1 << 1)# define RADEON_LVDS_PANEL_TYPE (1 << 2)# define RADEON_LVDS_PANEL_FORMAT (1 << 3)# define RADEON_LVDS_EN (1 << 7)# define RADEON_LVDS_DIGON (1 << 18)# define RADEON_LVDS_BLON (1 << 19)# define RADEON_LVDS_SEL_CRTC2 (1 << 23)#define RADEON_LVDS_PLL_CNTL 0x02d4# define RADEON_HSYNC_DELAY_SHIFT 28# define RADEON_HSYNC_DELAY_MASK (0xf << 28)#define RADEON_MAX_LATENCY 0x0f3f /* PCI */#define RADEON_MC_AGP_LOCATION 0x014c#define RADEON_MC_FB_LOCATION 0x0148#define RADEON_MC_STATUS 0x0150# define RADEON_MC_IDLE (1 << 2)# define R300_MC_IDLE (1 << 4)#define RADEON_DISPLAY_BASE_ADDR 0x23c#define RADEON_DISPLAY2_BASE_ADDR 0x33c#define RADEON_OV0_BASE_ADDR 0x43c#define RADEON_NB_TOM 0x15c#define R300_MC_INIT_MISC_LAT_TIMER 0x180#define RADEON_MCLK_CNTL 0x0012 /* PLL */# define RADEON_FORCEON_MCLKA (1 << 16)# define RADEON_FORCEON_MCLKB (1 << 17)# define RADEON_FORCEON_YCLKA (1 << 18)# define RADEON_FORCEON_YCLKB (1 << 19)# define RADEON_FORCEON_MC (1 << 20)# define RADEON_FORCEON_AIC (1 << 21)# define R300_DISABLE_MC_MCLKA (1 << 21)# define R300_DISABLE_MC_MCLKB (1 << 21)#define RADEON_MCLK_MISC 0x001f /* PLL */# define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1<<12)# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1<<13)# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14)# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15)#define RADEON_MDGPIO_A_REG 0x01ac#define RADEON_MDGPIO_EN_REG 0x01b0#define RADEON_MDGPIO_MASK 0x0198#define RADEON_MDGPIO_Y_REG 0x01b4#define RADEON_MEM_ADDR_CONFIG 0x0148#define RADEON_MEM_BASE 0x0f10 /* PCI */#define RADEON_MEM_CNTL 0x0140# define RADEON_MEM_NUM_CHANNELS_MASK 0x01# define RADEON_MEM_USE_B_CH_ONLY (1<<1)# define RV100_HALF_MODE (1<<3)# define R300_MEM_NUM_CHANNELS_MASK 0x03# define R300_MEM_USE_CD_CH_ONLY (1<<2)#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */#define RADEON_MEM_INIT_LAT_TIMER 0x0154#define RADEON_MEM_INTF_CNTL 0x014c#define RADEON_MEM_SDRAM_MODE_REG 0x0158#define RADEON_MEM_STR_CNTL 0x0150#define RADEON_MEM_VGA_RP_SEL 0x003c#define RADEON_MEM_VGA_WP_SEL 0x0038#define RADEON_MIN_GRANT 0x0f3e /* PCI */#define RADEON_MM_DATA 0x0004#define RADEON_MM_INDEX 0x0000#define RADEON_MPLL_CNTL 0x000e /* PLL */#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */#define R300_MC_IND_INDEX 0x01f8# define R300_MC_IND_ADDR_MASK 0x3f#define R300_MC_IND_DATA 0x01fc#define R300_MC_READ_CNTL_AB 0x017c# define R300_MEM_RBS_POSITION_A_MASK 0x03#define R300_MC_READ_CNTL_CD_mcind 0x24# define R300_MEM_RBS_POSITION_C_MASK 0x03#define RADEON_N_VIF_COUNT 0x0248#define RADEON_OV0_AUTO_FLIP_CNTL 0x0470# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010# define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040# define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300# define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000# define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000#define RADEON_OV0_COLOUR_CNTL 0x04E0#define RADEON_OV0_DEINTERLACE_PATTERN 0x0474#define RADEON_OV0_EXCLUSIVE_HORZ 0x0408# define RADEON_EXCL_HORZ_START_MASK 0x000000ff# define RADEON_EXCL_HORZ_END_MASK 0x0000ff00# define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000# define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000#define RADEON_OV0_EXCLUSIVE_VERT 0x040C# define RADEON_EXCL_VERT_START_MASK 0x000003ff# define RADEON_EXCL_VERT_END_MASK 0x03ff0000#define RADEON_OV0_FILTER_CNTL 0x04A0# define RADEON_FILTER_PROGRAMMABLE_COEF 0x0# define RADEON_FILTER_HC_COEF_HORZ_Y 0x1# define RADEON_FILTER_HC_COEF_HORZ_UV 0x2# define RADEON_FILTER_HC_COEF_VERT_Y 0x4# define RADEON_FILTER_HC_COEF_VERT_UV 0x8# define RADEON_FILTER_HARDCODED_COEF 0xf# define RADEON_FILTER_COEF_MASK 0xf#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0#define RADEON_OV0_FLAG_CNTL 0x04DC#define RADEON_OV0_GAMMA_000_00F 0x0d40#define RADEON_OV0_GAMMA_010_01F 0x0d44#define RADEON_OV0_GAMMA_020_03F 0x0d48#define RADEON_OV0_GAMMA_040_07F 0x0d4c#define RADEON_OV0_GAMMA_080_0BF 0x0e00#define RADEON_OV0_GAMMA_0C0_0FF 0x0e04#define RADEON_OV0_GAMMA_100_13F 0x0e08#define RADEON_OV0_GAMMA_140_17F 0x0e0c#define RADEON_OV0_GAMMA_180_1BF 0x0e10#define RADEON_OV0_GAMMA_1C0_1FF 0x0e14#define RADEON_OV0_GAMMA_200_23F 0x0e18#define RADEON_OV0_GAMMA_240_27F 0x0e1c#define RADEON_OV0_GAMMA_280_2BF 0x0e20#define RADEON_OV0_GAMMA_2C0_2FF 0x0e24#define RADEON_OV0_GAMMA_300_33F 0x0e28#define RADEON_OV0_GAMMA_340_37F 0x0e2c#define RADEON_OV0_GAMMA_380_3BF 0x0d50#define RADEON_OV0_GAMMA_3C0_3FF 0x0d54#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0#define RADEON_OV0_H_INC 0x0480#define RADEON_OV0_KEY_CNTL 0x04F4# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L# define RADEON_VIDEO_KEY_FN_NE 0x00000003L# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L# define RADEON_CMP_MIX_MASK 0x00000100L# define RADEON_CMP_MIX_OR 0x00000000L# define RADEON_CMP_MIX_AND 0x00000100L#define RADEON_OV0_LIN_TRANS_A 0x0d20#define RADEON_OV0_LIN_TRANS_B 0x0d24#define RADEON_OV0_LIN_TRANS_C 0x0d28#define RADEON_OV0_LIN_TRANS_D 0x0d2c#define RADEON_OV0_LIN_TRANS_E 0x0d30#define RADEON_OV0_LIN_TRANS_F 0x0d34#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L#define RADEON_OV0_P1_H_ACCUM_INIT 0x0488#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L?? 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