?? radeon_reg.h
字號(hào):
#define RADEON_OV0_P1_X_START_END 0x0494#define RADEON_OV0_P2_X_START_END 0x0498#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C#define RADEON_OV0_P3_X_START_END 0x049C#define RADEON_OV0_REG_LOAD_CNTL 0x0410# define RADEON_REG_LD_CTL_LOCK 0x00000001L# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L#define RADEON_OV0_SCALE_CNTL 0x0420# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L# define RADEON_SCALER_SIGNED_UV 0x00000010L# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L# define RADEON_SCALER_SOURCE_15BPP 0x00000300L# define RADEON_SCALER_SOURCE_16BPP 0x00000400L# define RADEON_SCALER_SOURCE_32BPP 0x00000600L# define RADEON_SCALER_SOURCE_YUV9 0x00000900L# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L# define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L# define RADEON_SCALER_CRTC_SEL 0x00004000L# define RADEON_SCALER_SMART_SWITCH 0x00008000L# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L# define RADEON_SCALER_DIS_LIMIT 0x08000000L# define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L# define RADEON_SCALER_INT_EMU 0x20000000L# define RADEON_SCALER_ENABLE 0x40000000L# define RADEON_SCALER_SOFT_RESET 0x80000000L#define RADEON_OV0_STEP_BY 0x0484#define RADEON_OV0_TEST 0x04F8#define RADEON_OV0_V_INC 0x0424#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4#define RADEON_OV0_Y_X_START 0x0400#define RADEON_OV0_Y_X_END 0x0404#define RADEON_OV1_Y_X_START 0x0600#define RADEON_OV1_Y_X_END 0x0604#define RADEON_OVR_CLR 0x0230#define RADEON_OVR_WID_LEFT_RIGHT 0x0234#define RADEON_OVR_WID_TOP_BOTTOM 0x0238/* first capture unit */#define RADEON_CAP0_BUF0_OFFSET 0x0920#define RADEON_CAP0_BUF1_OFFSET 0x0924#define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928#define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C#define RADEON_CAP0_BUF_PITCH 0x0930#define RADEON_CAP0_V_WINDOW 0x0934#define RADEON_CAP0_H_WINDOW 0x0938#define RADEON_CAP0_VBI0_OFFSET 0x093C#define RADEON_CAP0_VBI1_OFFSET 0x0940#define RADEON_CAP0_VBI_V_WINDOW 0x0944#define RADEON_CAP0_VBI_H_WINDOW 0x0948#define RADEON_CAP0_PORT_MODE_CNTL 0x094C#define RADEON_CAP0_TRIG_CNTL 0x0950#define RADEON_CAP0_DEBUG 0x0954#define RADEON_CAP0_CONFIG 0x0958# define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001# define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002# define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004# define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008# define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010# define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020# define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040# define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080# define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100# define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200# define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400# define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800# define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000# define RADEON_CAP0_CONFIG_VBI_EN 0x00002000# define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000# define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000# define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000# define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000# define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000# define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000# define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000# define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000# define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000# define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000# define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000# define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000# define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000# define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000# define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000# define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000# define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000#define RADEON_CAP0_ANC_ODD_OFFSET 0x095C#define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960#define RADEON_CAP0_ANC_H_WINDOW 0x0964#define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968#define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C#define RADEON_CAP0_BUF_STATUS 0x0970/* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 *//* #define RADEON_CAP0_XSHARPNESS 0x097C */#define RADEON_CAP0_VBI2_OFFSET 0x0980#define RADEON_CAP0_VBI3_OFFSET 0x0984#define RADEON_CAP0_ANC2_OFFSET 0x0988#define RADEON_CAP0_ANC3_OFFSET 0x098C#define RADEON_VID_BUFFER_CONTROL 0x0900/* second capture unit */#define RADEON_CAP1_BUF0_OFFSET 0x0990#define RADEON_CAP1_BUF1_OFFSET 0x0994#define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998#define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C#define RADEON_CAP1_BUF_PITCH 0x09A0#define RADEON_CAP1_V_WINDOW 0x09A4#define RADEON_CAP1_H_WINDOW 0x09A8#define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC#define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0#define RADEON_CAP1_VBI_V_WINDOW 0x09B4#define RADEON_CAP1_VBI_H_WINDOW 0x09B8#define RADEON_CAP1_PORT_MODE_CNTL 0x09BC#define RADEON_CAP1_TRIG_CNTL 0x09C0#define RADEON_CAP1_DEBUG 0x09C4#define RADEON_CAP1_CONFIG 0x09C8#define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC#define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0#define RADEON_CAP1_ANC_H_WINDOW 0x09D4#define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8#define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC#define RADEON_CAP1_BUF_STATUS 0x09E0#define RADEON_CAP1_DWNSC_XRATIO 0x09E8#define RADEON_CAP1_XSHARPNESS 0x09EC/* misc multimedia registers */#define RADEON_IDCT_RUNS 0x1F80#define RADEON_IDCT_LEVELS 0x1F84#define RADEON_IDCT_CONTROL 0x1FBC#define RADEON_IDCT_AUTH_CONTROL 0x1F88#define RADEON_IDCT_AUTH 0x1F8C#define RADEON_P2PLL_CNTL 0x002a /* P2PLL */# define RADEON_P2PLL_RESET (1 << 0)# define RADEON_P2PLL_SLEEP (1 << 1)# define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16)# define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)# define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)#define RADEON_P2PLL_DIV_0 0x002c# define RADEON_P2PLL_FB0_DIV_MASK 0x07ff# define RADEON_P2PLL_POST0_DIV_MASK 0x00070000#define RADEON_P2PLL_REF_DIV 0x002B /* PLL */# define RADEON_P2PLL_REF_DIV_MASK 0x03ff# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */# define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)# define R300_PPLL_REF_DIV_ACC_SHIFT 18#define RADEON_PALETTE_DATA 0x00b4#define RADEON_PALETTE_30_DATA 0x00b8#define RADEON_PALETTE_INDEX 0x00b0#define RADEON_PCI_GART_PAGE 0x017c#define RADEON_PIXCLKS_CNTL 0x002d# define RADEON_PIX2CLK_SRC_SEL_MASK 0x03# define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00# define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02# define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6)# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7)# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8)# define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)# define R300_DVOCLK_ALWAYS_ONb (1 << 10)# define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11)# define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12)# define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13)# define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14)# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15)# define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)# define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)# define R300_P2G2CLK_ALWAYS_ONb (1 << 18)# define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)# define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)#define RADEON_PLANE_3D_MASK_C 0x1d44#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */#define RADEON_PMI_DATA 0x0f63 /* PCI */#define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */#define RADEON_PMI_PMC_REG 0x0f5e /* PCI */#define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */#define RADEON_PMI_REGISTER 0x0f5c /* PCI */#define RADEON_PPLL_CNTL 0x0002 /* PLL */# define RADEON_PPLL_RESET (1 << 0)# define RADEON_PPLL_SLEEP (1 << 1)# define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16)# define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)# define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18)#define RADEON_PPLL_DIV_0 0x0004 /* PLL */#define RADEON_PPLL_DIV_1 0x0005 /* PLL */#define RADEON_PPLL_DIV_2 0x0006 /* PLL */#define RADEON_PPLL_DIV_3 0x0007 /* PLL */# define RADEON_PPLL_FB3_DIV_MASK 0x07ff# define RADEON_PPLL_POST3_DIV_MASK 0x00070000#define RADEON_PPLL_REF_DIV 0x0003 /* PLL */# define RADEON_PPLL_REF_DIV_MASK 0x03ff# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */#define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */#define RADEON_RBBM_GUICNTL 0x172c# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)#define RADEON_RBBM_SOFT_RESET 0x00f0# define RADEON_SOFT_RESET_CP (1?? 快捷鍵說(shuō)明
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